Christopher Warren, Chalmers, Quantum Technology

Opponent: Dr. Kevin Satzinger, Google Quantum AI, USA

The ultimate goal of quantum computing is to develop quantum algorithms and hardware that outperform any classical methods. However, noise in quantum systems hinders their direct implementation. Achieving universal quantum computing necessitates a fault-tolerant quantum computer, which requires thousands of physical qubits. This thesis explores whether our architecture can overcome these challenges and scale to the required number of qubits.

Superconducting quantum circuits are a highly developed platform for building quantum computers, leveraging advanced device design and fabrication technology that can scale rapidly to hundreds or thousands of qubits. Our architecture features fixed-frequency qubits connected by tunable couplers, operating at very low temperatures (∼10 mK). Qubits are controlled using radio-frequency electromagnetic fields, while magnetic fields parametrically modulate the couplers to enable interactions between qubits.

There are many axes along which one can scale to larger system sizes. The most commonly approached axis is by developing high-coherence quantum hardware. Coherence times determines the memory/operational lifetime of quantum information. Our fabrication has allowed us to achieve multi-qubit processors with coherence times over 100 µs. However, coherence times are not without a context, as we also require fast gate times. The control of quantum hardware is a second direction towards scaling; minimizing the time to implement a logical operation relative to the coherence times of the device. In our processors, we are able to implement two-qubit operations with < 1% error in 250 ns, with which we implemented two quantum algorithms to infer the performance of our architecture. Moreover we improve the readout accuracy in our architecture by artificially extending the lifetime of the qubit during measurement through a state shelving scheme.

A third, often overlooked axis for scaling quantum hardware is expanding the native logical gate set. Typically, quantum processors use a limited set of operations. We developed a technique to implement a native three-qubit gate by simultaneously applying our two-qubit operations, expanding the gate set without altering the architecture. This demonstrated coherence-limited performance and enabled faster generation of highly entangled states compared to using only two-qubit operations.

Although our parametric architecture offers advantages for scaling, significant challenges remain, particularly in maintaining coherence, minimizing crosstalk, and ensuring device yield as qubit numbers increase. This thesis explores the limitations and obstacles in scaling superconducting quantum processors, using experimental data and theoretical models. We address key issues with the parametric gate, such as frequency crowding and crosstalk, and discuss the fabrication tolerances needed to scale to a 100-qubit system.