Present research at Compound Semiconductor Electron Device Laboratory, Tokyo Institute of Technology

Abstract: The first research target is GaN devices for high frequency. The introduction of partial high-k film between gate and drain is explained based on the calculation and the experiment for higher breakdown voltage at short gate-drain length. Mitigation of the short channel effect by surface treatment is also described. The second target is a lateral heterojunction bipolar transistor. The theoretical calculation for the pnp transistor and experimental trial by selective growth will be explained.

Bio: Yasuyuki Miyamoto received D.Eng. degree from the Tokyo Institute of Technology, Tokyo, Japan, in 1988. He is currently working as a Professor at Tokyo Institute of Technology. He worked as a Consultant at AT&T Bell Laboratories, from 1994 to 1995. His current research interests include III-V semiconductor electronic devices and nanometer fabrication technology. Prof. Miyamoto is a Fellow of JSAP. He received the IEICE Electronics Society Award in 2013.