Title: Quantum Circuit Compilation: Approaches to Hardware Constraints and Optimization
Overview
- Date:Starts 29 August 2025, 14:00Ends 29 August 2025, 15:00
- Location:
- Language:English
Abstract: This seminar presents three projects addressing key challenges in quantum circuit compilation—the process of transforming abstract quantum algorithms into executable instructions on physical quantum hardware. As quantum processors scale toward practical applications, efficient compilation becomes critical for managing hardware constraints while preserving algorithmic performance.
Project A: Time-Multiplexed Qubit Control (Primary Focus)
I investigate the feasibility of time-multiplexing for scalable superconducting qubit control, where multiple qubits share control lines to reduce the unsustainable linear scaling of wiring requirements. Developing a compilation algorithm to minimize serialization overhead, I systematically benchmark performance across 5×5 grids, 11×11 grids, and IBM's 127-qubit heavy-hexagon architecture using both random circuits and quantum algorithms. Key findings include logarithmic rather than linear scaling of overhead with qubits per switch—arising from structural interactions between single- and two-qubit gates—and manageable runtime increases (sub-10 microseconds for most algorithms with 2-4 qubits per switch). This analysis demonstrates time-multiplexing as a viable path toward scalable quantum computing, with detailed circuit modeling revealing how gate serialization can be optimized through strategic ordering.
Project B: Optimal Qubit Routing via Constraint Programming
I explore constraint programming techniques for optimal qubit routing solutions, addressing the NP-hard problem of mapping logical two-qubit gates onto limited physical connectivity graphs.
Project C: Deep Reinforcement Learning for Qubit Routing
I develop AlphaZero-based approaches for qubit routing, combining Monte Carlo tree search with neural network guidance to discover routing strategies that surpass current heuristics.
Together, these projects span the compilation pipeline from hardware-aware gate scheduling to connectivity optimization, addressing fundamental bottlenecks that limit quantum algorithm execution on near-term and future quantum processors.
Supervisor: Associate Professor Anton Frisk Kockum
Discussion leader: Assistant Professor Mizanur Rahaman
Examiner: Professor Göran Johansson