Certifiable System-on-Chip for Safety Critical Industrial Applications

Purpose and goal: The project aims to address a gap in the security model of hardware/software systems where software is designed and certified to a identified criticality level, hardware is developed to certain standards including full design assurance flows, while the interface between hardware and software is missing a contract.
This has the effect that applications rely on software to provide security functions, but there is no formal guarantee that the software function is able to do that when running on a hardware platform. Expected results and effects: The project will directly influence the design of a next-generation European space-grade microprocessor that is developed under the product name GR7xV. The project results will immediately affect the IP core building blocks of Cobham Gaisler, provide a path for commercialization for Chalmer´s Network-on-Chip technology, and strengthen atsec´s position in security evaluations of system-on-chip design. The project will also increase awareness about the gap in between hardware and software when building secure systems. Approach and implementation: The project will start with a specification phase that will identify a reduced version of the GR7xV SoC design and identify security objectives. The design will then be implemented in an FPGA prototype and through an iterative workflow, the design will be updated in parallel with a security evaluation towards the defined security objectives.

Partner organizations

  • Cobham Gaisler AB (Private, Sweden)
  • atsec Information Security (Private, USA)
Start date 01/06/2021
End date 31/05/2023

Page manager Published: Sat 11 Dec 2021.