Solid-state electronics based on utilizing the electron spin degree of freedom for storing and processing information can pave the way for next-generation spin-based computing. However, the realization of spin communication between multiple devices in complex spin circuit geometries, essential for practical applications, still remained challenging.
"Our experimental demonstration of spin communication in large area CVD graphene spin circuit architectures is a milestone towards large-scale integration and development of spin-logic and memory technologies”, says Saroj Dash (to the left), associate professor and group leader, who supervised the research project.
Dmitrii Khokhriakov, PhD student at the Quantum Device Physics Laboratory at Chalmers University of Technology, carved complicated graphene Y-junction and Hexa-arm spin circuit architectures utilizing nanofabrication techniques compatible with industrial manufacturing processes.
The researchers demonstrate that the spin-polarized current can be effectively communicated between the magnetic memory elements in different 2D graphene circuit architectures. They take advantage of extraordinary long-distance spin transport observed in commercially available wafer-scale CVD graphene with transport lengths exceeding 34 μm at room temperature. In addition, the researchers also demonstrate that by engineering the graphene channel geometry and orientation of spin polarization, the symmetric and antisymmetric spin precession signals can be tuned in a precise manner.
This research at Chalmers is funded by the EU Graphene Flagship and the Swedish Research Council (VR).
Illustration: Dmitrii Khokhriakov
Photo of Saroj Prasad Dash: Oscar Mattsson