The gallium nitride (GaN) high electron mobility transistor (HEMT) has become a frequent choice of technology in many applications, particularly in mobile telecommunication networks and radar applications. GaN offers the unique combination of a wide bandgap and a high electron saturation velocity, which brings the advantage of a transistor technology that can provide both high output power and gain at high frequency.
Despite having reached a relatively high level of maturity, challenges related to the GaN HEMT remain unsolved. These include so-called short-channel effects (SCE), which appear for downscaled transistor dimensions at high drain voltage and prevent efficient pinching of the device. Another issue is the nonlinear output response of the HEMT, which leads to reduced efficiency and significantly complicates the work of the power amplifier designer.
Recently, the finFET topology has attracted attention when implemented on GaN HEMT heterostructures. The GaN finFET is identical to the HEMT, except for the presence of etched trenches in the drain-source region, with the intermediate spacings referred to as “fins”. With this approach, the gate surrounds the channel from three sides, thus improving the gate control.
In this work, the potential of the GaN finFET in terms of improved linearity and reduced SCE was investigated. This was performed by TCAD simulations, fabrication and characterization of finFETs with different device geometries. For comparison, regular HEMTs were simulated and processed in the same batch. The simulations indicated that finFETs are effective in reducing SCE. The degree of SCE correlated to the fin width, i.e., narrower fins led to less SCE. No clear improvement in linearity was seen for the finFETs as compared to the HEMTs. On the other hand, the finFETs exhibited higher transconductance.
The characterization results of the fabricated devices confirmed the trends observed regarding SCE. The most significant difference was seen when comparing the finFETs with the HEMTs. The SCE, as measured by DIBL, dropped from 80 mV/V to about 10 - 25 mV/V for the finFETs. No conclusions could be drawn for the linearity since the pinch-off voltage near zero volts prevented a full view of the transconductance peak. A drawback of the finFET topology was a simultaneous drop in the output current.
Student project presentation
11 June, 2021, 14:00
11 June, 2021, 15:00