The Cadence Academic Network was launched in 2007 by Cadence EMEA. The aim is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected European universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems. The Cadence Academic Network, therefore, significantly support and improve the universities activities.
The Academic Network became an integral part of CDNLive! where universities and industry members are offered a knowledge exchange platform in order to demonstrate scientific achievements, present ideas and establish further collaborations.
The Cadence Academic Network manages a page for discussion and opportunities on LinkedIn, and information can also be found on the Cadence Academic Network webpage. On LinkedIn, the groups are moderated by the lead institutions of the Academic Network, ensuring a constant flow of reviewed information relevant to academia.
The Computer and Network Systems division is using Cadence technology extensively in both teaching and research.
In the context of the Cadence Academic Network, we below list some of our activities in research and education that harness EDA tools from Cadence. For further information, contact the head of the VLSI Research Group Professor Per Larsson-Edefors.
- Cadence tools for both cell-based and custom ASIC flows are extensively used
in our research; see the publications list for the Computer and Network Systems division.
- ls, a design space exploration environment for energy-efficient processors,
was presented as a
poster at CDNLive EMEA 2010. The FlexTools toolchain helps
the designer configure the FlexCore processor architecture so it can execute the
application's C code in an energy-efficient manner. Mary parts of the toolchain,
for example, scheduler, architectural simulator and RTL generator, have been
developed in our research projects. However, without the access to several
commercial EDA tools, for example, Cadene Encounter, it wouldn't have been
possible to implement an ASIC backend flow inside FlexTools.
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