Image of mikrochip.

Principles for computing memory devices

A new project at Chalmers, funded by the Foundation for Strategic Research, aims to present a proposal on how processing devices can be integrated into the memory circuits of future computers.
For more than five decades, the speed at which computers get things done has been able to increase exponentially thanks to the fact that it has been possible to increase the number of transistors on a computer chip at the same pace. At this point, it is becoming challenging to fit more transistors on each chip, and at the same time the computing tasks are becoming increasingly data intensive, with everything from self-driving vehicles to analysis of massive data sets. This questions conventional wisdom how computers are built and calls for new solutions.

Per StenströmIn today's technology, data is sent back and forth between the memory and computer chips, which costs both time and processing power (energy). In the project PRIDE: Principles for computing memory devices, Per Stenström, professor in the Computer Engineering division at the Department of Computer Science and Engineering, will investigate how parallelism and memory allocation can be handled in an energy-efficient and transparent way. “The vision is a completely new type of parallel computers, where the computing devices are integrated in the memory devices”, says Per Stenström.

With a new programming model for software to be developed in the project, the hope is that in 10 years it will be possible to increase the speed at which computers get things done a hundred times and the memory capacity by ten times on each computer chip. With today's technology, this approach would yield 10 teraFLOP (10 ^ 13 floating point operations per second) and 100 GB of memory on a computer chip. With the solution planned in PRIDE, it would be possible to build computer chips approaching 1 petaFLOP (10 ^ 15 floating point operations per second) and 1 TB of memory in ten years from now.

About the project

The project starts on January 1, 2021 and is funded with 28 million over 5 years by the Foundation for Strategic Research, as a part of the research program Computing and Hardware for ICT Infrastructures, which distributes close to SEK 200 million in framework grants. The call is aimed at hardware for the next generation of wireless communication (6G), accelerated computing power and more energy-efficient ICT.

PRIDE will from the beginning initiate collaborations with commercial stakeholders among Swedish companies, and work in synergy with the EuroHPC project The European Processor Initiative in which Chalmers participates.

Contact:

Professor Per Stenström, Computer Engineering division.
E-mail: per.stenstrom@chalmers.se

Photo of Per Stenström: Anna-Lena Lundqvist

Published: Tue 27 Oct 2020.