Events: Data- och informationsteknik events at Chalmers University of TechnologyThu, 27 Jan 2022 11:24:56 +0100 scale battery production - environmental benefits and new challenges<p>OOTO Café, café, Sven Hultins Plats 2, Johanneberg Science Park 2</p><p>NOTE! Due to the pandemic, we are holding the seminar on a new date and time. We are back, after the Christmas holidays, with the new year&#39;s first Friday seminar. Welcome!Time and place: Café Ooto, Guldhuset, Johanneberg Science Park, 28 January, 12:30-14:00. In this seminar Anders Nordelöf, leader of the SEC theme Electromobility in society and researcher at Technology Management and Economics at Chalmers University of Technology, will give us different perspectives and an exciting discussion on a hot topic: Large scale battery production - environmental benefits and new challenges.</p><div><br /></div> <div><a href=""><img class="ms-asset-icon ms-rtePosition-4" src="/_layouts/images/icgen.gif" alt="" /> <span style="background-color:initial">R</span><span style="background-color:initial">egister to the seminar here</span></a></div> <div><br /></div> <div><strong> </strong><span style="background-color:initial"><strong>Program</strong></span></div> <div><br /></div> <div><ul><li>12:30, Welcome Tomas Kåberger, Chalmers Energy Area of Advance</li> <li>L<span style="background-color:initial">arge scale battery production - environmental benefits and new challenges, Anders Nordelöf.</span></li> <li>13<span style="background-color:initial">: 05-14:00, Mingle.</span></li></ul></div> <div><span style="background-color:initial"><br /></span></div> <div><span style="background-color:initial">Related:<br /></span><a href="/sv/personal/redigera/Sidor/anders-nordelof.aspx"><img class="ms-asset-icon ms-rtePosition-4" src="/_layouts/images/ichtm.gif" alt="" />Read more about Anders Nordelöf.</a><span style="background-color:initial"><br /><div><a href="/en/areas-of-advance/energy/news/Pages/Contributes-to-the-EUs-work-to-electrify-the-transport-sector.aspx"><img class="ms-asset-icon ms-rtePosition-4" src="/_layouts/images/ichtm.gif" alt="" /><span style="background-color:initial">C</span><span style="background-color:initial">ontributes to the EU’s work to electrify the transport sector<br /></span></a><a href="" style="outline:0px"><img class="ms-asset-icon ms-rtePosition-4" src="/_layouts/images/icgen.gif" alt="" />Swedish Electromobility Centre</a><br /><span></span><a href="/en/areas-of-advance/Transport/profile-areas/Pages/Sustainable-Vehicle-Technologies.aspx"><img class="ms-asset-icon ms-rtePosition-4" src="/_layouts/images/ichtm.gif" alt="" />Sustainable Vehicle Technologies​</a><br /></div> <br /><br /><br /></span></div> Ramon Currius, Computer Science and Engineering<p>Online</p><p>​Realistic Real-Time Rendering of Global Illumination and Hair througc</p><div><br /></div> Over the last decade, machine learning has gained a lot of traction in many areas, and with the advent of new GPU models that include acceleration hardware for neural network inference, real-time applications have also started to take advantage of these algorithms.<br /><br /> In general, machine learning and neural network methods are not designed to run at the speeds that are required for rendering in high-performance real-time environments, except for very specific and typically limited uses. For example, several methods have been developed recently for denoising of low quality pathtraced images, or to upsample images rendered at lower resolution, that can run in real-time. <br /><br /> This thesis collects two methods that attempt to improve realistic scene rendering in such high-performance environments by using machine learning. <br /><br /> Paper I presents a neural network application for compressing surface lightfields into a set of unconstrained spherical gaussians to render surfaces with global illumination in a real-time environment. <br /><br /> Paper II describes a filter based on a small convolutional neural network that can be used to denoise hair rendered with stochastic transparency in real time Bastys, Computer Science and Engineering<p>Online</p><p>​Principled Flow Tracking in IoT and Low-Level Applications</p><br /><div>Significant fractions of our lives are spent digitally, connected to and dependent on Internet-based applications, be it through the Web, mobile, or IoT. All such applications have access to and are entrusted with private user data, such as location, photos, browsing habits, private feed from social networks, or bank details.</div> <br /> In this thesis, we focus on IoT and Web(Assembly) apps. We demonstrate IoT apps to be vulnerable to attacks by malicious app makers who are able to bypass the sandboxing mechanisms enforced by the platform to stealthy exfiltrate user data. We further give examples of carefully crafted WebAssembly code abusing the semantics to leak user data.<br /><br /> We are interested in applying language-based technologies to ensure application security due to the formal guarantees they provide. Such technologies analyze the underlying program and track how the information flows in an application, with the goal of either statically proving its security, or preventing insecurities from happening at runtime. As such, for protecting against the attacks on IoT apps, we develop both static and dynamic methods, while for securing WebAssembly apps we describe a hybrid approach, combining both.<br /><br /> While language-based technologies provide strong security guarantees, they are still to see a widespread adoption outside the academic community where they emerged. In this direction, we outline six design principles to assist the developer in choosing the right security characterization and enforcement mechanism for their system. We further investigate the relative expressiveness of two static enforcement mechanisms which pursue fine- and coarse-grained approaches for tracking the flow of sensitive information in a system. Finally, we provide the developer with an automatic method for reducing the manual burden associated with some of the language-based enforcements. Mahmood, Computer Science and Engineering<p>Online</p><p>​​​A Framework for Seamless Variant Management and Incremental Migration to a Software Product-Line​</p><strong>​​</strong><div><strong>Context:</strong> Software systems often need to exist in many variants in order to satisfy varying customer requirements and operate under varying software and hardware environments. These variant-rich systems are most commonly realized using cloning, a convenient approach to create new variants by reusing existing ones. Cloning is readily available, however, the non-systematic reuse leads to difficult maintenance. An alternative strategy is adopting platform-oriented development approaches, such as Software Product-Line Engineering (SPLE). SPLE offers systematic reuse, and provides centralized control, and thus, easier maintenance. However, adopting SPLE is a risky and expensive endeavor, often relying on significant developer intervention. Researchers have attempted to devise strategies to synchronize variants (change propagation) and migrate from clone&amp;own to an SPL, however, they are limited in accuracy and applicability. Additionally, the process models for SPLE in literature, as we will discuss, are obsolete, and only partially reflect how adoption is approached in industry. Despite many agile practices prescribing feature-oriented software development, features are still rarely documented and incorporated during actual development, making SPL-migration risky and error-prone. <div><strong><br /></strong></div> <div> <strong>Objective:</strong> The overarching goal of this PhD is to bridge the gap between clone&amp;own and software product-line engineering in a risk-free, smooth, and accurate manner. Consequently, in the first part of the PhD, we focus on the conceptualization, formalization, and implementation of a framework for migrating from a lean architecture to a platform-based one. </div> <div><strong><br /></strong></div> <div> <strong>Method:</strong> Our objectives are met by means of (i) understanding the literature relevant to variant-management and product-line migration and determining the research gaps (ii) surveying the dominant process models for SPLE and comparing them against the contemporary industrial practices, (iii) devising a framework for incremental SPL adoption, and (iv) investigating the benefit of using features beyond PL migration; facilitating model comprehension. </div> <div><strong><br /></strong></div> <div> <strong>Results:</strong> Four main results emerge from this thesis. First, we present a qualitative analysis of the state-of-the-art frameworks for change propagation and product-line migration. Second, we compare the contemporary industrial practices with the ones prescribed in the process models for SPL adoption, and provide an updated process model that unifies the two to accurately reflect the real practices and guide future practitioners. Third, we devise a framework for incremental migration of variants into a fully integrated platform by exploiting explicitly recorded metadata pertaining to clone and feature-to-asset traceability. Last, we investigate the impact of using different variability mechanisms on the comprehensibility of various model-related tasks. </div> <div><strong><br /></strong></div> <div> <strong>Future work:</strong> As ongoing and future work, we aim to integrate our framework with existing IDEs and conduct a developer study to determine the efficiency and effectiveness of using our framework. We also aim to incorporate safe-evolution in our operators.</div></div> Ramakrishnan Geethakumari, Computer Science and Engineering<p>Online</p><p>​​​Reconfigurable-Hardware Accelerated Stream Aggregation</p>​​<div>High throughput and low latency stream aggregation is essential for many applications that analyze massive volumes of data in real-time. Incoming data need to be stored in a single sliding-window before processing, in cases where incremental aggregations are wasteful or not possible at all. However, storing all incoming values in a single-window puts tremendous pressure on the memory bandwidth and capacity. GPU and CPU memory management is inefficient for this task as it introduces unnecessary data movement that wastes bandwidth. FPGAs can make more efficient use of their memory but existing approaches employ only on-chip memory and therefore, can only support small problem sizes (i.e. small sliding windows and number of keys) due to the limited capacity. This thesis addresses the above limitations of stream processing systems by proposing techniques for accelerating single sliding-window stream aggregation using FPGAs to achieve line-rate processing throughput and ultra low latency. <div>It does so first by building accelerators using FPGAs and second, by alleviating the memory pressure posed by single-window stream aggregation. The initial part of this thesis presents the accelerators for both windowing policies, namely, tuple- and time- based, using Maxeler's DataFlow Engines (DFEs) which have a direct feed of incoming data from the network as well as direct access to off-chip DRAM. Compared to state-of-the-art stream processing software system, the DFEs offer 1-2 orders of magnitude higher processing throughput and 4 orders of magnitude lower latency. </div> <div>The later part of this thesis focuses on alleviating the memory pressure due to the various steps in single-window stream aggregation. Updating the window with new incoming values and reading it to feed the aggregation functions are the two primary steps in stream aggregation. The high on-chip SRAM bandwidth enables line-rate processing, but only for small problem sizes due to the limited capacity. The larger off-chip DRAM size supports larger problems, but falls short on performance due to lower bandwidth. In order to bridge this gap, this thesis introduces a specialized memory hierarchy for stream aggregation. It employs Multi-Level Queues (MLQs) spanning across multiple memory levels with different characteristics to offer both high bandwidth and capacity. In doing so, larger stream aggregation problems can be supported at line-rate performance, outperforming existing competing solutions. Compared to designs with only on-chip memory, our approach supports 4 orders of magnitude larger problems. Compared to designs that use only DRAM, our design achieves up to 8x higher throughput.</div> <div>Finally, this thesis aims to alleviate the memory pressure due to the window-aggregation step. Although window-updates can be supported efficiently using MLQs, frequent window-aggregations remain a performance bottleneck. This thesis addresses this problem by introducing StreamZip, a dataflow stream aggregation engine that is able to compress the sliding-windows. StreamZip deals with a number of data and control dependency challenges to integrate a compressor in the stream aggregation pipeline and alleviate the memory pressure posed by frequent aggregations. In doing so, StreamZip offers higher throughput as well as larger effective window capacity to support larger problems. StreamZip supports diverse compression algorithms offering both lossless and lossy compression to fixed- as well as floating- point numbers. Compared to designs using MLQs, StreamZip lossless and lossy designs achieve up to 7.5x and 22x higher throughput, while improving the effective memory capacity by up to 5x and 23x, respectively.</div></div> Parthasarathy, Computer Science and Engineering<p>Online</p><p>​Deep learning based simulation for automotive software development</p> risk and long-term AI safety<p>Online Zoom</p><p>​Short lecture series on AI risk and long-term AI safety. February 21-25, 2022. ​</p><strong>​<br /></strong><span><strong>Time: February 21-25, 2022</strong></span><p><span lang="EN-US"><strong>Place: Online, Zoom - register to get the link</strong><br /></span><span style="background-color:initial"><strong>S</strong></span><span style="background-color:initial"><strong>peaker: Olle Häggström<br /><a href="" target="_blank"><img class="ms-asset-icon ms-rtePosition-4" src="/_layouts/images/icgen.gif" alt="" />Register here</a></strong></span></p> <p><span lang="EN-US"><br /></span></p> <p><span lang="EN-US">This six-hour lecture series (in English) will treat basics and recent developments in <strong>AI risk and long-term AI safety</strong>. The lectures are meant to be of interest to Ph.D. students and researchers in AI-related fields, but no particular prerequisites will be assumed. Some of the basics will be taken from my 2021 book <a href="" target="_blank">Tänkande maskiner​</a>, but the field is developing rapidly and most of what I say in the lectures will go beyond what I did in the book.</span></p> <p><span style="background-color:initial">An</span><span style="background-color:initial"> ambition will be to post recordings of the lectures at CHAIR’s YouTube channel quickly after each lecture, so that participants missing a lecture will have the chance to catch up before the next one.</span></p> <p><span style="background-color:initial">The three two-hour lectures are scheduled as follows:</span></p> <p><span style="background-color:initial">1. Monday, February 21 at 15.15-17.00: </span><strong style="background-color:initial">How and why things might go wrong</strong><br /></p> <p><span lang="EN-US">2. Wednesday, February 23 at 15.15-17.00: <strong>Timelines, natural language processors and oracle AI<br /></strong></span></p> <p><span lang="EN-US">3. Friday, February 25 at 10.00-11.45: <strong>Research directions in AI alignment<br /></strong></span></p> <div><span lang="EN-US" style="margin:0px;padding:0px;border:0px;font:inherit;vertical-align:baseline;color:inherit"><b><br /></b></span></div> Eldstål-Ahrens, Computer Science and Engineering<p>Online.</p><p>​​​Lossy and Lossless Compression Techniques to Improve the Utilization of Memory Bandwidth and Capacity</p>​​<div>Main memory is a critical resource in modern computer systems and is in increasing demand. An increasing number of on-chip cores and specialized accelerators improves the potential processing throughput but also calls for higher data rates and greater memory capacity. In addition, new emerging data-intensive applications further increase memory traffic and footprint. On the other hand, memory bandwidth is pin limited and power constrained and is therefore more difficult to scale. Memory capacity is limited by cost and energy considerations. This thesis proposes a variety of memory compression techniques as a means to reduce the memory bottleneck. These techniques target two separate problems in the memory hierarchy: memory bandwidth and memory capacity. In order to reduce transferred data volumes, lossy compression is applied which is able to reach more aggressive compression ratios. A reduction of off-chip memory traffic leads to reduced memory latency, which in turn improves the performance and energy efficiency of the system. To improve memory capacity, a novel approach to memory compaction is presented. <div><br /></div> <div> The first part of this thesis introduces Approximate Value Reconstruction (AVR), which combines a low-complexity downsampling compressor with an LLC design able to co-locate compressed and uncompressed data. Two separate thresholds limit the error introduced by approximation. For applications that tolerate aggressive approximation in large fractions of their data, in a system with 1GB of 1600MHz DDR4 per core and 1MB of LLC space per core, AVR reduces memory traffic by up to 70%, execution time by up to 55%, and energy costs by up to 20% introducing at most 1.2% error in the application output.<br /><br /> The second part of this thesis proposes Memory Squeeze (MemSZ), introducing a parallelized implementation of the more advanced Squeeze (SZ) compression method. Furthermore, MemSZ improves on the error limiting capability of AVR by keeping track of life-time accumulated error. An alternate memory compression architecture is also proposed, which utilizes 3D-stacked DRAM as a last-level cache. In a system with 1GB of 800MHz DDR4 per core and 1MB of LLC space per core, MemSZ improves execution time, energy and memory traffic over AVR by up to 15%, 9%, and 64%, respectively.<br /><br /> The third part of the thesis describes L2C, a hybrid lossy and lossless memory compression scheme. L2C applies lossy compression to approximable data, and falls back to lossless if an error threshold is exceeded. In a system with 4GB of 800MHz DDR4 per core and 1MB of LLC space per core, L2C improves on the performance of MemSZ by 9%, and energy consumption by 3%.<br /><br /> The fourth and final contribution is FlatPack, a novel memory compaction scheme. FlatPack is able to reduce the traffic overhead compared to other memory compaction systems, thus retaining the bandwidth benefits of compression. Furthermore, FlatPack is flexible to changes in block compressibility both over time and between adjacent blocks. When available memory corresponds to 50% of the application footprint, in a system with 4GB of 800MHz DDR4 per core and 1MB of LLC space per core, FlatPack increases system performance compared to current state-of-the-art designs by 36%, while reducing system energy consumption by 12%.</div></div>