Evaluation and optimization of interconnects in CMOS devices for millimeter wave applications
The last decades down scaling of device geometries for microprocessors in CMOS, Complementary Metal Oxide Semiconductor, technology has lead to very high transit frequencies, beyond 200 GHz, for these transistors. This has made it possible to use standard CMOS processes also for micro and millimeter wave designs even up to and beyond 60 GHz. However the metal connections from the intrinsic device to the circuit level (from bottom metal and up to, usually top metal level) are introducing parasitics and are also of great concern then it comes to power amplifiers. So far the layout of these interconnects have been made based on a best guess estimate and no thorough analysis have been published with trade offs and dependencies of different ways to make the interconnects.
The main objectives is to;
Complete, or almost complete, courses from a masters program in electronics
Mattias Ferndahl, Email: email@example.com, Phone: 031-7728930
interconnects-CMOS-devices.pdf 550.02 kb
Last modified: March 25, 2009
Responsible for this page: Hans Hjelmgren