Departments' graduate courses
Course start and periodicity may vary. Please see details for each course for up-to-date information. The courses are managed and administered by the respective departments. For more information about the courses, how to sign up, and other practical issues, please contact the examiner or course contact to be found in the course information.
Formal Verification of Hardware: Why, When, How?
- Course code: FDAT105
- Course higher education credits: 7.5
- Department: COMPUTER SCIENCE AND ENGINEERING
- Graduate school: Computer Science and Engineering
- Course start: 2017-03-20
- Course end: 2017-05-26
- Course is normally given: Not regular.
- Language: The course will be given in English
The course consist of one lecture (2 x 45 minutes) per week, 2-3 assignments, and a fairly significant project that can be done individually or in a small team.
Cost of verification and how to pick the approach with highest return-of-investment.
- Introduction to modern hardware design and the verification challenge
- Traditional verification methods with their strength and weaknesses.
- High-level overview of formal verification methods and the history of the field
- Underlying technologies:
- Ordered binary decision diagrams
- SAT solvers
- Model checking
- Symbolic simulation
- Formal equivalence verification
- Reference model verification
- Property verification
- Typical formal verification methodology:
- Specification creation and maintenance.
- Initial wiggling of design
- First formal verification attempts
- Debugging of failed verification attempts
- Environment assumption creation
- Generalization of verification results
- Invariant properties creation
- Regression of proofs, or how to make proofs robust to changing designs.
- Alternative verification methodologies
- Designer driven design exploration
- Integrated design and verification
- Goals of verification:
Conference and journal articles made available on line.