The use of transistors in our daily lives is
ubiquitous, with transistors being found in everything from smart phones, TV’s,
e-readers and computers. However, these transistors made from amorphous silicon
require a variety of energy intensive batch manufacturing techniques such as
material deposition and patterning steps, which take place under high vacuum
and at high temperature. Additionally, the fabrication of amorphous silicon
transistors is wasteful in terms of materials as several subtractive
lithographic patterning and mask steps are required which limit manufacturing
throughput. For this reason, each year there is a continued drive to shrink the
size of a single transistor, so that more transistors can fit onto a piece of
silicon wafer and thus this helps to lower the cost of an individual
transistor. Whilst this means that the cost of an individual is very low, the
actual cost per unit area is very high. This presents an opportunity for
organic semiconductors to be used instead as they can be formulated into inks
and cheaply deposited via non energy intensive solution processing techniques
such as ink jet and gravure printing. This enables the manufacture of large
area, low temperature, high throughput organic field effect transistors (OFETs)
which not only enables them to be low cost but also enables the development of
flexible circuitry, as the lower temperatures used in the production process
will enable plastic substrates to be used. A number of possible applications
for these cheap, flexible OFETs have been envisaged ranging from radio
frequency identification tags, that could be used in supermarkets instead of
bar codes to flexible backplanes in active matrix displays.
A number of transistor
device architectures can be employed depending on the order of material
deposition. The most common architectures are Figure 1 a) top contact, bottom
gate b) bottom contact, bottom gate c) top contact, top gate and d) bottom
contact, top gate. In all these device architectures the underlying principle
is the same. OFETs are typically either p-type or n-type depending on the
organic semiconductor used. In the case of a p-type device, the charges are
holes which are injected and extracted from the semiconductor material via the
source and drain electrodes. Upon applying a negative gate voltage holes are
injected into the semiconductor and accumulate at the semiconductor/ dielectric
interface. Here they form an accumulation layer and are subsequently
transported to the drain electrode upon application of an electric field
between the source and the drain. By modulating the gate voltage the transistor
can be turned ON or OFF.
The focus of this
project is to develop new conjugated polymers with higher charge carrier
mobilities and better ambient stability for use in high performance OFET
devices.
Figure
1: OFET device architectures a) top contact, bottom gate. b) bottom-contact,
bottom-gate. c) top-contact, top-gate. d) bottom-contact, top-gate.