Evaluation and optimization of interconnects in CMOS devices for millimeter wave applications
The last decades down scaling of device geometries for microprocessors in CMOS, Complementary Metal Oxide Semiconductor, technology has lead to very high transit frequencies, beyond 200 GHz, for these transistors. This has made it possible to use standard CMOS processes also for micro and millimeter wave designs even up to and beyond 60 GHz. However the metal connections from the intrinsic device to the circuit level (from bottom metal and up to, usually top metal level) are introducing parasitics and are also of great concern then it comes to power amplifiers. So far the layout of these interconnects have been made based on a best guess estimate and no thorough analysis have been published with trade offs and dependencies of different ways to make the interconnects.
The main objectives is to;
From 3D/2D EM simulations and measured data make an analysis as how the interconnects should be made in order to get extrinsic performance as close as possible to the intrinsic performance.
A study on how the different parasitics influence the performance, e.g. unilateral gain as function of gate resistance and/or source drain capacitance.
To analyze the dependence of these parasitics on device geometry and layout (including the interconnects), and suggest an optimized layout/geometry for power applications.
Complete, or almost complete, courses from a masters program in electronics with a direction towards microwaves and preferably some knowledge of 3D/2D EM simulators like HFSS, EMDS, Momentum, etc.