The exponential growth of mobile communication systems and the increased demand for high data rates necessitate the use of available mm-wave spectrum. Therefore highly anticipated 5G standard is going to use such frequencies for this purpose. The frequency synthesizer is a key component in such a wireless communication system.
The design of high performance phase locked loop (PLL) frequency synthesizer is a crucial task. The building blocks of the PLL are first to be designed. A system model is then to be constructed to calculate PLL characteristics and the output phase noise. Finally, the system is to be designed and implemented in a commercial state of the art CMOS SOI technology.
We expect the candidates to have a strong background in analogue and digital electronic circuit theory as well as microwave circuit design. Experience in CAD tools such as ADS and cadence is highly desired. In return the candidates will receive theoretical as well as practical support in the different project phases.
 E. Hegazi, H. Sjoland and A. A. Abidi, "A filtering technique to lower LC oscillator phase noise," in IEEE JSSC, 2001.
A. Mazzanti and P. Andreani, "Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise," in IEEE JSSC, 2008
M.Babaie, and R. B. Staszewski, "An Ultra-Low Phase Noise Class-F2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability," in IEEE Journal of Solid-State Circuits, 2015.
M.Babaie, and R. B. Staszewski, "A 57.9-to-68.3 GHz 24.6 mW Frequency SynthesizerWith In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology," in IEEE Journal of Solid-State Circuits, 2014.
W. Egan “Frequency synthesis by phase lock”, Wiley, 1999
30hp Master Thesis work at Microwave Electronics Laboratory/MC2
Two students are needed for this project
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