Ryman, Erik; Emrich, Anders; Andersson, Stefan; Riesbeck, Johan; Svensson, Lars; Larsson-Edefors, Per: 3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry. Proceedings of the 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011, San Jose, 19-21 September 2011, ISBN/ISSN: 978-145770222-8

Jeppson, Kjell; Peterson, Lena; Svensson, Lars; Larsson-Edefors, Per: Implementing Constructive Alignment in a CDIO-oriented Master’s Program in Integrated Electronic System Design. Proceedings of European Workshop on Microelectronics Education, pp. 135-140.

Ryman, Erik; Larsson-Edefors, Per; Svensson, Lars; Emrich, Anders; Andersson, Stefan: A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application. European Space Agency Microwave Technology and Techniques Workshop,

Ryman, Erik; Emrich, A.; Embretsen, J.; Riesbeck, J.; Andersson, S.; Larsson-Edefors, Per; Svensson, Lars: Digital Cross-Correlators: Two Approaches. Proceedings of Gigahertz Symposium,

Svensson, Lars; Pihl, Johnny; Andersson, Daniel; Larsson-Edefors, Per: On-chip Power Supply Noise and Its Implications on Timing. Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 389-392. ISBN/ISSN: 978-145030012-4

Andersson, Daniel; Nilsson, Björn; Pihl, Johnny; Svensson, Lars; Larsson-Edefors, Per: Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid. Proceedings of 13th Workshop on Signal Propagation on Interconnects (SPI),

Ryman, Erik; Larsson-Edefors, Per; Emrich, Anders; Svensson, Lars: High-Performance 64-input Cross-Correlator. Swedish System-on-Chip Conference (SSoCC),

Svensson, Lars; Pihl, Johnny; Andersson, Daniel; Nilsson, Björn; Larsson-Edefors, Per: Towards Supply-Grid-Based Derating of Timing Margins. Proceedings of 13th Workshop on Signal Propagation on Interconnects (SPI),

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Journal of Signal Processing Systems, 57 (1) pp. 5-19.

Andersson, Daniel; Kristiansson, Simon; Svensson, Lars; Larsson-Edefors, Per; Jeppson, Kjell: Noise Interaction Between Power Distribution Grids and Substrate. Proceedings of Intl Symp. on Quality Electronic Design (ISQED), pp. 84-90.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. Proceedings of Intl Symp. on Quality Electronic Design (ISQED), pp. 663-669.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation. IET Computers & Digital Techniques, 2 (4) pp. 265-274.

Jeppson, Kjell; Peterson, Lena; Svensson, Lars; Bengtsson, Lars; Larsson-Edefors, Per: A New Master's Program in Integrated Electronic System Design. European Workshop on Microelectronics Education, EWME 2008 (Budapest)

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis. IEEE Workshop on Signal Propagation on Interconnects,

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Sheeran, Mary; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Stenström, Per: Exposed Datapath for Efficient Computing. 2007 HiPEAC Workshop on Reconfigurable Computing,

Drazdziulis, Mindaugas; Larsson-Edefors, Per; Svensson, Lars: Overdrive Power-Gating Techniques for Total Power Minimization. IEEE Computer Society Annual Symposium on VLSI,

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. IEEE SAMOS 2007, pp. 18-25.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Interconnect Characterization Flow for Minimal-Segment Model Selection. Norchip Conference,

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Sheeran, Mary; Stenström, Per: Exposed Datapath for Efficient Computing. Göteborg : Chalmers University of Technology.

Svensson, Lars; Athas, William; Lal, Rajat: Power-efficient, pulsed driving of capacitive loads to controllable voltage levels .

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Accounting for the Skin Effect during Repeater Insertion. ACM Great Lakes Symposium on VLSI (GLSVLSI),

Svensson, Lars; Lindoff, Bengt: Determining correlations of received sequences to multiple known sequences in a communications system.

Svensson, Lars; Athas, William: Line reflection reduction with energy-recovery driver.

Svensson, Lars; Athas, William; Koller, Jeffrey: System and method for power-efficient charging and discharging of a capacitive load from a single source.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Frequency-Dependent Effects in RLC Interconnects. Swedish System-on-Chip Conference,

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: On Skin Effect in On-Chip Interconnects. Intl Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 463-470.

Dam, H.; Nordebo, S.; Svensson, Lars: Design of minimum-phase digital filters as the sum of two allpass functions using the cepstrum technique. IEEE Transactions on Signal Processing, 51 (3) pp. 726-731.

Eckerbert, Daniel; Svensson, Lars; Larsson-Edefors, Per: A Mixed-Mode Delay-Locked Loop Architecture. Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, 13-15 October 2003, pp. 261-263. ISBN/ISSN: 0-7695-2025-1

Hughes, John; Jeppson, Kjell; Larsson-Edefors, Per; Sheeran, Mary; Stenström, Per; Svensson, Lars: FlexSoC: Combining Flexibility and Efficiency in SoC Designs. Proceedings of 21st Norchip Conference, Riga, Latvia pp. 52-55.

Larsson-Edefors, Per; Eckerbert, Daniel; Eriksson, Henrik; Svensson, Lars: Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. Proceedings of IEEE Computer Society Annual Symposium on VLSI,