Professor

Visiting address:
Rännvägen 6, EDIT-building

I am teaching and performing research in the Department of Computer Science and Engineering at the Chalmers University of Technology. My research interests include computer systems design, advanced computer architecture and micro-architecture, reconfigurable computing, hardware/software co-design, Embedded Systems, VLSI design, and computer systems testing.

Currently my research focuses on dynamic techniques to manage contemporary distributed memory hierarchies and heterogeneous multicore systems, application specific acceleration, and low overhead reliability techniques. All the above topics are in the context of the emerging CMOS technology trends when the quality of the available transistors is deteriorating while their quantity on a single chip keeps scaling up. These trends combined with the severe power dissipation constraints of digital logic require novel, holistic hardware-software approaches and expose new challenges to computer systems designers. A possible simplification of the problem is how to transform the available transistor quantity into affordable (in respect to power dissipation per unit area) quality.

My current projects are

1. ProMSys: Programmable Multicore Systems (VR, Sweden) (aiming at dynamic hardware/software energy efficient techniques to improve data locality, load balancing and synchronization of future parallel computing systems)
2. ENCORE: ENabling technologies for a programmable many-CORE (ICT-2009.3.6 Computing Systems) (focus on dynamically customizable, highly efficient, parallel memory architectures while considering the 3D stacking opportunities)
3. DeSyRe: on-Demand System Reliability (FP7-ICT-2011-7, Computing Systems) (advanced architecture for scalable, energy efficient, reliable computing systems)
4.  FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (FP7-ICT-2011-7, Computing Systems) (the main focus is on low overhead architectural extensions for partially reconfigurable high-performance computers)

In the past I successfully completed several research projects on various topics targeting energy efficient and high-performance computing systems. The most prominent examples were:

1. Scalable Computer Architecture (SARC, Integrated Project FP6/Future and Emerging technologies, 8.5Mln Euro completed in 2010). I was the project coordinator and in addition I led a team of PhD students in Delft performing research on energy efficient application specific acceleration, customizable memory systems and technology aware networks on chip design.
2. Holistic Approach to reconfigurable real time embedded systems (hArtes, Integrated Project FP6/Embedded Systems, completed in 2009). My team of three PhD students performed research on efficient runtime management of reconfigurable computing systems and custom architecture for immersive audio processing.
3. Reconfigurable Acceleration for the Google application (Google Inc, USA). The team of one PostDoc and four Master of Science students focused on seamless integration of Reconfigurable Acceleration in an AMD Hypertransport based, general purpose workstation for streaming applications.

In the context of computer systems security I contributed to the initial hardware design of the RFID Guardian, a project performed together with the group of Prof. Andrew Tanenbaum at the Vrije Universiteit of Amsterdam. With a team of Phd, Master and Bachelor students under my supervision designed and implemented the onboard computer system (hardware and software) and the reliable distributed ground station (using the world-wide web) for the Delfi-C3 project (a student satellite with the Department of Airspace Engineering, launched in 2008 and fully operational to date).
I also worked on various hardware designs for Cryptographic Algorithms processing (e.g., AES, Elliptic Curves and RSA). I always had several projects together with the Industry. With RISCURE in Delft we worked on Java smart card security evaluation, hardware countermeasures and hardware platforms for attestation.

With Fox-IT we investigated various options suitable for their next generation network forensic systems. Before joining Academia in 2002 I was involved in the design of various safety critical computing systems (medical, industrial and home automation) and crypto processors for secure web systems. For example at Pijnenburg Microelectronics and Software and CPS, I contributed to the design of the very first smart card reader for Internet banking in the Netherlands (project in order of ABN Amro, the biggest Dutch bank, products still in use by many customers).

Another research topic worked out by one of my PhD students and me was on tiny highly reliable, architecture for implantable medical devices. The “redundant” hardware resources (aka dark silicon) provided by the contemporary CMOS technology are used for application specific power/performance efficient functions but most importantly for built-in provisions for system dependability and fault tolerance.

The Smart implantable Medical Systems (SiMS) project was initiated in close collaboration with Erasmus medical center, Leiden University Medical Center in the Netherlands and University Hospital Antwerp in Belgium. The SiMS project is still very vibrant and is currently run at Erasmus Medical center where my former PhD student is a PostDoc.

My research has been supported by the European Commission (Framework programs FP6 and FP7 / Computing Systems and Future and Emerging Technologies objectives), the Swedish research council (VR), the Technology Foundation STW in the Netherlands, Google Inc. USA, the point.one Technology Association and CenterNovem / BSIK in the Netherlands.

Awards

• Parallel computation methods and architectures senior research position, Swedish research council (VR), the Council for natural and engineering sciences, September, 2010
• ACM/SIGARCH 24th International Conference on Supercomputing (ICS'10) Tsukuba, Japan, June 2010. Best paper award
• Ramon y Cayal incorporación doctor, Ministerio de Sciencia en Innovacion, Spain, 2010
• Google Inc unrestricted gift of $60,000 for research on Reconfigurable Computing (2009)
• USENIX/SAGE Large Installation System Administration conference (LISA 2006), Washington DC, USA, December 2006. Best paper award
• Workshop in Information Security Theory and Practices 2007 (WiSTP'07), Heraklion, Greece, May 2007. Best paper award
• Prontomail Screen Phone P112. Design & Engineering Showcase Award, Consumer Electronics Show (CES), Las Vegas, USA, 1999

Talks

• Efficient GPGPU Memory Management for the Masses, Multicore Architectures and Their Effective Operation 2012, June 28, 2012, Barcelona, Spain
• Sequence Alignment Application Model for Multi-and Manycore Architectures, 25th Int. conference on Information Technologies (InfoTech-2011), Varna, Bulgaria, September 15, 2011
• Alleviating On-chip Shared Memory Bank Conflicts in Data Parallel Accelerators, Electronics 2011, Sozopol, Bulgaria, September 14, 2011
• The SARC Task-centric Architecture and Programming Model, University of Amsterdam (UvA), the Netherlands, May 30, 2011
• Is reconfigurable acceleration promising for Google Applications?, Google Inc, Mountain View, USA, Feb. 25, 2010
• HiPEAC addresses the long-term multicore research challenges, HiPEAC 8-th Industrial workshop, Wroclaw, Poland, Oct. 26, 2009
• SARC - the future scalable heterogeneous architecture and its programing model, keynote at the 2-nd Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG), Paphos, Cyprus, January 25, 2009
• Embedded Architectures for Bioinformatics, Workshop Frontiers of High Performance Embedded Computing, Bangalore, India, January 14 – 16, 2009
• Polymorphic processors and toolchains, Workshop Frontiers of High Performance Embedded Computing, Bangalore, India, January 14 – 16, 2009
• The MOLEN Polymorphic Processor and its Dedicated Tool Chain, University of Victoria, British Columbia, Canada, Sept, 2008
• SARC- the status after 2 years, CASTNESS Artist2 NoE workshop, Rome, January 2008
• SARC, Session on relevant EU projects, HiPEAC 4-th Industrial Workshop, Cambridge, UK, November 2007
• The MOLEN polymorphic processor and its dedicated toolchain, UC Riverside and UC Irvine, October 2007
• SARC: Systematic scalable approach to systems design: From small energy critical embedded systems to large scale networked data servers, Workshop on Directions in FPGAs and Reconfigurable Systems: Design, Programming and Technologies for adaptive heterogeneous Systems-on-Chip and their European Dimensions, DATE Conference 2007, Nice, France, April 2007
• Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers, Guest lecture, Department of Electronic systems, Aalborg Universiteit, Denmark, April 2007
• SARC overview, Computing Architectures and Software Tools for Numerical Embedded Scalable Systems workshop and school, CASTNESS, Rome, Italy, January 2007
• Reconfigurable processors and programming paradigms, guest lecture, Technical University of Sofia, Bulgaria, May 2005
• Trusted Computing Platform, a quick look under the hood, AEGEE Symposium What they don’t tell us; privacy and security on the computer, Utrecht, Netherlands, April 2004