Cadence Academic Network
In the context of the Cadence Academic Network, we below list some of our activities in research and education that harness EDA tools from Cadence. For further information, contact the head of the VLSI Research Group Professor Per Larsson-Edefors.
- Cadence tools for both cell-based and custom ASIC flows are extensively used in our research, see the webpage and the publications list for the VLSI Research Group for a general overview.
- FlexTools, our design space exploration environment for energy-efficient processors, was presented as a poster at the CDNLive! EMEA workshop 2010. The FlexTools toolchain helps the designer configure the FlexCore processor architecture so it can execute the application's C code in an energy-efficient manner. Mary parts of the toolchain, for example, the scheduler, the architectural simulator and the RTL generator, have been developed in our research projects. However, without the access to several commercial EDA tools, for example, Cadene Encounter, it wouldn't have been possible to implement an ASIC backend flow inside FlexTools.
Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134
September 30, 2011
Responsible for this page: