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Atmel collaborationIn our ongoing research collaboration with Atmel Norway, on power integrity analysis of the AVR microprocessors, we have obtained some results that are best presented as animations; thus, this special project page. Below we provide the result of a power grid simulation, as well as the master's theses by Björn Nilsson and Martin Olsson that detail different aspects of the analysis methodology and a few papers that describe parts of our analysis methodology.
If you are a master student looking for an interesting thesis proposal, contact us for project proposals. 
Atmel web presentation
Atmel has produced a web presentation that provides not only several animations of varying power grid voltages, but also some information on the context for the simulations. The web presentation is too large (35 MB) for the CPS web system, so you need to follow this link to view the presentation.
http://www.cse.chalmers.se/~perla/atmel/presentati ...
SPI'07
"Toward a systematic sensitivity analysis of on-chip power grids using factor analysis", by D. A. Andersson, L. "J" Svensson, and P. Larsson-Edefors, Proceedings of IEEE Workshop Signal Propagation on Interconnects, 13-16 May 2007.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumbe ...
ISQED'08
"Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach", by D. A. Andersson, L. "J" Svensson, and P. Larsson-Edefors, Proceedings of 9th International Symposium on Quality Electronic Design, 17-19 March 2008.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumbe ...
SPI'09 - 1
"Supply voltage drop study considering on-chip self inductance of a 32-bit processor's power grid", by D. A. Andersson, B. Nilsson, J. Pihl, L. "J" Svensson and P. Larsson-Edefors, Proceedings of IEEE Workshop Signal Propagation on Interconnects, 12-15 May 2009.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumbe ...
SPI'09 - 2
"Towards supply-grid-based derating of timing margins" by L. "J" Svensson, J. Pihl, D. A. Andersson, B. Nilsson and P. Larsson-Edefors, Proceedings of IEEE Workshop Signal Propagation on Interconnects, 12-15 May 2009.
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isn ...
GLSVLSI'10
"On-chip power supply noise and its implications on timing" by L. "J" Svensson, J. Pihl, D. A. Andersson, and P. Larsson-Edefors, Proceedings of the 20th Great Lakes Symposium on VLSI, 2010.
http://portal.acm.org/citation.cfm?id=1785481.1785 ...
SPI'11
"Extracting vectors from application traces for power integrity analysis" by M. Olsson, J. Pihl, D. A. Andersson, and P. Larsson-Edefors, Proceedings of IEEE Workshop Signal Propagation on Interconnects, 8-11 May 2011.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumbe ...
Last modified:
October 02, 2011
Responsible for this page: Per Larsson-Edefors |  |
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