Azhar, Muhammad Waqar; Själander, Magnus; Hasan, Ali; Vijayashekar, Akshay; Hoang-Thanh, Tung; Ansari, Kashan Khurshid; Larsson-Edefors, Per: Viterbi Accelerator for Embedded Processor Datapaths. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP),

Själander, Magnus; McKee, Sally A; Brauer, Peter; Engdal, David; Vajda, Andras: An LTE Uplink Receiver PHY Benchmark and Subframe-Based Power Management. Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software,

Bardizbanyan, Alen; Själander, Magnus; Larsson-Edefors, Per: Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp. 322-325 . ISBN/ISSN: 978-076954385-7

Frolov, Nick; Själander, Magnus; Larsson-Edefors, Per; McKee, Sally A: A SAT-Based Compiler for FlexCore. Göteborg : Chalmers University of Technology.

Goel, Bhavishya; Själander, Magnus; McKee, Sally A; Spiliopoulos, Vasileios; Keramidas, Georgios; Kaxiras, Stefanos; Efstathiou, Konstantinos: Infrastructures for Measuring Power. Göteborg : Chalmers University of Technology.

Goumas, Georgios; McKee, Sally A; Själander, Magnus; Gross, Thomas R.; Karlsson, Sven; Probst, Christian W.; Zhang, Lixin: Adapt or Become Extinct!. Proceedings of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era, pp. 46-51. ISBN/ISSN: 978-1-4503-0708-6

Själander, Magnus; McKee, Sally A; Goel, Bhavishya; Brauer, Peter; Engdal, David; Vajda, Andras: Power-Aware Resource Scheduling in Base Stations. Proceedings of the 19th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems Singapore; 25 July 2011 through 27 July 2011, pp. 462-465. ISBN/ISSN: 978-0-7695-4430-4

Subramaniyan, Kasyab P.; Ryman, Erik; Själander, Magnus; Hoang-Thanh, Tung; Islam, Mafijul; Larsson-Edefors, Per: FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation. Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), pp. 37-40. ISBN/ISSN: 978-1-4244-9136-0

Wong, S.; Brandon, A.; Anjam, F.; Seedorf, R.; Giorgi, R.; Yu, Z.; Puzovic, N.; McKee, Sally A; Själander, Magnus; Carro, L.; Keramidas, G.: Early results from ERA embedded reconfigurable architectures. 9th IEEE International Conference on Industrial Informatics, INDIN 2011, Lisbon, 26-29 July 2011, pp. 816-822. ISBN/ISSN: 978-145770434-5

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Transactions on Circuits and Systems I, 57 (12) pp. 3073-3081.

Hoang-Thanh, Tung; Jälmbrant, Ulf; der Hagopian, Erik; Subramaniyan, Kasyab P.; Själander, Magnus; Larsson-Edefors, Per: Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect. Proceedings of IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP),

Ryman, Erik; Subramaniyan, Kasyab P.; Hoang-Thanh, Tung; Islam, Mafijul; Själander, Magnus; Larsson-Edefors, Per: FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation. CDNLive! EMEA,

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements. Reconfigurable Architectures Workshop, Proceedings of IEEE International Parallel & Distributed Processing Symposium (IPDPS),

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture. Proceedings of IEEE Intl SoC Conference (SoCC), pp. 119-122. ISBN/ISSN: 978-1-4244-5220-0

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture. Swedish System-on-Chip Conference (SSoCC),

Jälmbrant, Ulf; der Hagopian, Erik; Själander, Magnus; Larsson-Edefors, Per: Design-Time Scheduling for Processor Exploration. Swedish System-on-Chip Conference (SSoCC),

Kimfors, Patrik; Broman, Niklas; Haraldsson, Andreas; Subramaniyan, Kasyab P.; Själander, Magnus; Eriksson, Henrik; Larsson-Edefors, Per: Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree. Proceedings of IEEE International Conference of Electronics, Circuits and Systems,

Schilling, Thomas; Själander, Magnus; Larsson-Edefors, Per: Scheduling for an Embedded Architecture with a Flexible Datapath. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 151-156. ISBN/ISSN: 978-1-4244-4408-3

Själander, Magnus; Larsson-Edefors, Per: Multiplication Acceleration through Twin Precision. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17 (9) pp. 1233-1246.

Thuresson, Martin; Själander, Magnus; Stenström, Per: A Flexible Code-Compression Scheme using Partitioned Look-Up Tables.. 4th Int. Conf. on High-Performance and Embedded Architectures and Compilers (HiPEAC),

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Journal of Signal Processing Systems, 57 (1) pp. 5-19.

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: Double Throughput MAC for Performance Enhancement of the FlexCore Processor. Swedish System-on-Chip Conference,

Islam, Mafijul; Själander, Magnus; Stenström, Per: Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors. Microprocessors and Microsystems, Elsevier, 42 (4) pp. 183-196.

Själander, Magnus; Terechko, Andrei; Duranton, Marc: A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. Euromicro Conference on Digital System Design: Architecture, Methods, and Tools,

Själander, Magnus: Efficient and Flexible Embedded Systems and Datapath Components. Göteborg : Chalmers University of Technology. Diss. ISBN/ISSN: 978-91-7385-137-4

Själander, Magnus; Larsson-Edefors, Per: High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree. Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS),

Själander, Magnus; Larsson-Edefors, Per: The Case for HPM-Based Baugh-Wooley Multipliers. Göteborg : Chalmers University of Technology.

Thuresson, Martin; Själander, Magnus; Stenström, Per: A Flexible Code Compression Scheme using Partitioned Look-Up Tables. Göteborg : Chalmers University of Technology.

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Sheeran, Mary; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Stenström, Per: Exposed Datapath for Efficient Computing. 2007 HiPEAC Workshop on Reconfigurable Computing,

Själander, Magnus; Larsson-Edefors, Per; Björk, Magnus: A Flexible Datapath Interconnect for Embedded Applications. IEEE Computer Society Annual Symposium on VLSI, pp. 15-20.

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. IEEE SAMOS 2007, pp. 18-25.

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Sheeran, Mary; Stenström, Per: Exposed Datapath for Efficient Computing. Göteborg : Chalmers University of Technology.

Brinck, Martin; Eklund, Kristian; Själander, Magnus; Larsson-Edefors, Per: An Efficient FFT Engine Based on Twin-Precision Computation. Swedish System--on-Chip Conference,

Eriksson, Henrik; Larsson-Edefors, Per; Sheeran, Mary; Själander, Magnus; Johansson, Daniel; Schölin, Martin: Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity. IEEE Intl Symposium on Circuits and Systems (ISCAS),

Själander, Magnus: Efficient Reconfigurable Multipliers Based on the Twin-Precision Technique. Göteborg : Chalmers University of Technology.

Själander, Magnus; Drazdziulis, Mindaugas; Larsson-Edefors, Per; Eriksson, Henrik: A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating. IEEE International Symposium on Circuits and Systems, pp. 1654-7.

Själander, Magnus; Larsson-Edefors, Per: A Power-Efficient and Versatile Modified-Booth Multiplier. Swedish System-on-Chip Conference,

Själander, Magnus; Eriksson, Henrik; Larsson-Edefors, Per: An Efficient Twin-Precision Multiplier. International Conference on Computer Design (ICCD), pp. 30-33.