Negi, Anurag; Titos, Ruben; Acacio, Manuel; Garcia, Jose; Stenström, Per: Pi-TM: Pessimistic Invalidation for Scalable Hardware Transactional Memory.. 18th IEEE International Symposium on High-Performance Computer Architecture,

Negi, Anurag: Adaptable Hardware Transactional Memory Protocols. Göteborg : Chalmers University of Technology.

Negi, Anurag; Titos-Gil, R.; Acacio, M. E.; García, J. M.; Stenström, Per: Eager meets lazy: The impact of write-buffering on hardware transactional memory. Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011, pp. 73-82. ISBN/ISSN: 978-076954510-3

Negi, Anurag; Stenström, Per; Titos Gil, Ruben; Acacio, Manuel E.; Garcia, Jose: Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. The 20th International Conference on Parallel Architectures and Compilation Techniques, 2011, (10-14 Oct. 2011) pp. 203-204. ISBN/ISSN: 978-076954566-0

Negi, Anurag; Titos, Ruben; Acacio, Manuel; Garcia, Jose; Stenström, Per: The Impact of Non-coherent on Lazy HardwareTransactional Memory Systems. APDCM 2011 (in conj. with 2011 IEEE IPDPS),

Titos Gil, Ruben; Negi, Anurag; Acacio, Manuel E.; Garcia, Jose M.; Stenström, Per: ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. International Conference on Supercomputing, 2011, pp. 53-62. ISBN/ISSN: 978-1-4503-0102-2

Negi, Anurag; Waliullah, Mrida Mohammad; Stenström, Per: LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems. 2nd IEEE Int. Forum of Next-Generation Multicore/Many-Core Technologies (IFMT’2010), ISBN/ISSN: 978-145030008-7

Negi, Anurag; Waliullah, Mrida Mohammad; Stenström, Per: LV*: A Low Complexity Lazy Versioning HTM Infrastructure. Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010, pp. 231-240. ISBN/ISSN: 978-142447938-2