Bardizbanyan, Alen; Gavin, Peter; Whalley, David; Själander, Magnus; Larsson-Edefors, Per; McKee, Sally A; Stenström, Per: Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB). Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27,

Arelakis, Angelos; Stenström, Per: A Case for a Value-Aware Cache. IEEE Computer Architecture Letters,

Arjemach, Adria; Negi, Anurag; Cristal, Adrian; Unsal, Osman; Stenström, Per: Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory. TRANSACT ,

Transactions on Architectures and Code Optimizations. Koen De Bosschere, Per Stenström [editor(s)]. Los Angeles : ACM.

Dubois, Michel; Annavaram, Murali; Stenström, Per: Parallel Computer Organization and Design. Cambridge : Cambridge University Press. ISBN/ISSN: 91-44-26461-5

Manivannan, Madhavan; Negi, Anurag; Stenström, Per: A Data Forwarding Scheme for Task-based Programming Models. Proceedings of the Fifth Swedish Workshop on Multicore Computing,

Negi, Anurag; Titos Gil, Ruben; Acacio, Manuel; Garcia, Jose; Stenström, Per: Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. 18th IEEE International Symposium on High Performance Computer Architecture (;New Orleans, LA; February 25-29 2012, pp. 141-151. ISBN/ISSN: 978-146730824-3

Negi, Anurag; Armejach, Adria; Cristal, Adrian; Unsal, Osman; Stenström, Per: Transactional Prefetching: Narrowing the Window of Contention in Hardware Transaction Memory. International Conference on Parallel Architectures and Compiler Techniques (PACT),

Negi, Anurag; Armejach, A.; Cristal, A.; Unsal, O.S.; Stenström, Per: Transactional prefetching: Narrowing the window of contention in hardware transactional memory. 21st International Conference on Parallel Architectures and Compilation Techniques, PACT 2012. Minneapolis, MN, 19 - 23 September 2012, pp. 181-190.

Waliullah, M.M.; Stenström, Per: Removal of Conflicts in Hardware Transactional Memory Systems. International Journal of Parallel Programming ,

Chen, Guancheng; Stenström, Per: Diagnosing Critical Section Bottlenecks in Multithreaded Applications. 2011 MULTIPROG workshop (in conjunction with 2011 HiPEAC Conference),

Islam, Mafijul; Stenström, Per: A Unified Approach to Eliminate Memory Accesses Early. Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11, Taipei, 9-14 October 2011, pp. 55-64. ISBN/ISSN: 978-145030713-0

Islam, Mafijul; Stenström, Per: A Unified Scheme to Cancel Memory Accesses Early. Göteborg : Chalmers University of Technology.

Manivannan, Madhavan; Juurlink, Ben; Stenström, Per: Implications of Merging Phases on Scalability of Multi-core Architectures. Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011, pp. 622-631. ISBN/ISSN: 978-076954510-3

Manivannan, Madhavan; Juurlink, Ben; Stenström, Per: Implications of Merging Phases on Scalability of Multicore Architectures. Internantional Conference on Supercomputing (ICS),

Negi, Anurag; Titos-Gil, R.; Acacio, M. E.; García, J. M.; Stenström, Per: Eager meets lazy: The impact of write-buffering on hardware transactional memory. Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011, pp. 73-82. ISBN/ISSN: 978-076954510-3

Negi, Anurag; Stenström, Per; Titos Gil, Ruben; Acacio, Manuel E.; Garcia, Jose: Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. The 20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011 Galveston, TX; 10 October 2011 through14 October 20111, (Article number 6113816) pp. 203-204. ISBN/ISSN: 978-076954566-0

Negi, Anurag; Titos, Ruben; Acacio, Manuel; Garcia, Jose; Stenström, Per: The Impact of Non-coherent on Lazy HardwareTransactional Memory Systems. APDCM 2011 (in conj. with 2011 IEEE IPDPS),

Negi, Anurag; Titos Gil, Ruben; Acacio, Manuel E.; García, José M.; Stenström, Per: The impact of non-coherent buffers on lazy hardware transactional memory systems. IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 25th IEEE International Parallel and Distributed Processing Symposium, Workshops and Phd Forum, IPDPSW 2011; Anchorage, AK; 16 May 2011 through 20 May 2011, pp. 700-707 . ISBN/ISSN: 978-076954385-7

Stenström, Per: Method and mechanism for cache compaction and bandwidth reduction.

Transaction on Architectures and Code Optimization. Per Stenström, Koen De Bosschere [editor(s)].

Transactions on High Performance and Embedded Architectures and Compilers - Vol 4. Per Stenström [editor(s)]. Heidelberg : Springer Verlag.

Transactions on High-Performance Architectures and Compilers Vol 3. Per Stenström [editor(s)]. Heidelberg : Springer Verlag.

Titos-Gil, R.; Negi, Anurag; Acacio, M. E.; García, J. M.; Stenström, Per: ZEBRA: A data-centric, hybrid-policy hardware transactional memory design. Proceedings of the International Conference on Supercomputing, ICS 2011. Tucson, 31 May-4 June 2011, pp. 53-62 . ISBN/ISSN: 978-145030102-2

Vajda, Andras; Stenström, Per: Coherence-Less Model for Shared-Memory, Speculative Multi-core Processors. FASPP’11 (in conj. with 2011 ACM/IEEE ISCA),

Vajda, Andras; Stenström, Per: Hints Based Speculative Execution for Exploiting Probabilistic Parallel Execution. . WANDS’11 (in conjunction with 2011 IEEE PACT),

Waliullah, M.M.; Stenström, Per: Classification and Elimination of Conflicts in Hardware-Transactional Memory Systems. 23rd International Conference on Computer Architecture and High Performance Computing (SBAC-PAD 2011), pp. 96-103 . ISBN/ISSN: 978-076954573-8

Waliullah, M.M.; Stenström, Per: Techniques for Reduction of Conflicts in Hardware Transactional Memory.. 2011 MULTIPROG Workshop (in conjunction with the HiPEAC conference),

Busck, Alexander; Engbom, Mikael; Stenström, Per; Warg, Fredrik: Generating and Comparing Memory Access Ranges for Speculative Throughput Computing.

Cristal, Adrian; Drepper, Ulrich; Diestelhorst, Stephan; Dragojevic, Alexander; Fetzer, Christoph; Felber, Pascal; Gramoli, Vincent; Guerraoui, Rachid; Harmanci, Derin; Hohmuth, Michael; Hur, Ibrahim; Kapalka, Michal; Korland, Guy; Maldonado, Walther; Marlier, Patrick; Nowack, Martin; Pohlack, Martin; Riegel, Torvald; Rivi`ere, Etienne; Shavit, Nir; Stenström, Per; Tomi´c, Saˇsa; Unsal, Osman: The VELOX Transactional Memory Stack. IEEE Micro,

Ekman, Magnus; Stenström, Per: System and Method for Memory Compression.

Islam, Mafijul; Stenström, Per: A Unified Approach to Cancel Memory Instructions Early. Göteborg : Chalmers University of Technology.

Islam, Mafijul; Stenström, Per: Characterization and Exploitation of Narrow-Width Loads:The Narrow-Width Cache Approach. IEEE/ACM International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES 2010), pp. 227-236. ISBN/ISSN: 978-160558903-9

Islam, Mafijul; Stenström, Per: Characterization and Exploitation of Silent Loads. 3rd Swedish Workshop on Multicore Computing (MCC'10),

Manivannan, Madhavan; Stenström, Per: Implications of Serial Reduction Phases in Data Mining Applications on Scalability of Multi-core Designs. Proceedings of the Third Swedish Workshop on Multicore Computing,

Negi, Anurag; Waliullah, Mrida Mohammad; Stenström, Per: LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems. 2nd IEEE Int. Forum of Next-Generation Multicore/Many-Core Technologies (IFMT’2010), ISBN/ISSN: 978-145030008-7

Negi, Anurag; Waliullah, Mrida Mohammad; Stenström, Per: LV*: A Low Complexity Lazy Versioning HTM Infrastructure. Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010, pp. 231-240. ISBN/ISSN: 978-142447938-2

Stenström, Per; Chen, Guancheng: Diagnosing Serialization Bottlenecks in Multi-threaded Applications on Multi-core Processors. Proceedings of the Third Swedish Workshop on Multicore Computing,

Vajda, Andras; Stenström, Per: Semantic Information Driven Speculative Execution. ACM/IEEE W on New Direction in Computer Architectre,

Vajda, András; Stenström, Per: Sematic based speculative parallel execution.. Third IEEE Workshop on Parallel Execution of Sequential Programs on Multicore Architectuers (PESPMA 2010),

Waliullah, Mrida Mohammad; Stenström, Per: Simple Performance Optimization Techniques for Hardware Transactional Memory Systems. Proceedings of the Third Swedish Workshop on Multicore Computing,

Chen, Jianwei; Dubois, Michel; Stenström, Per: SimWattch and Learn. IEEE Potentials, 28 (1) pp. 17-23.

Hollmann, Jochen; Stenström, Per: Using Hoarding to Increase the Availability in Shared File Systems. 2009 IEEE ISIS,

Islam, Mafijul; McKee, Sally A; Stenström, Per: Cancellation of Loads that Return Zero Using Zero-Value Caches. In Proceedings of the 23rd ACM International Conference on Supercomputing (ICS'09), New York, USA, June 8-12, 2009 ,

Islam, Mafijul; McKee, Sally A; Stenström, Per: Zero-Value Caches: Cancelling Loads that Return Zero. Göteborg : Chalmers University of Technology.

Islam, Mafijul; Stenström, Per: Zero-Value Caches: Cancelling Loads that Return Zero.. IEEE Parallel Architectures and Compilation Techniques (PACT), pp. 237-245 . ISBN/ISSN: 978-0-7695-3771-9

Stenström, Per: Method and System for process Memory Management.

Transactions on High-Performance Embedded Architectures and Compilers. Per Stenström [editor(s)]. Hedielberg : Springer Verlag.

Thuresson, Martin; Själander, Magnus; Stenström, Per: A Flexible Code-Compression Scheme using Partitioned Look-Up Tables.. 4th Int. Conf. on High-Performance and Embedded Architectures and Compilers (HiPEAC),

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Journal of Signal Processing Systems, 57 (1) pp. 5-19.

Vajda, And´ras; Stenström, Per: Semantic information driven speculative execution. IEEE/ACM MICRO "New Directions in Computer Architecture",

Waliullah, Mrida Mohammad; Stenström, Per: Schemes for avoiding starvation in transactional memory systems. Concurrency and Computation-Practice & Experience, 21 (7) pp. 859-873.

Bardine, Alessandro; Foglia, PieroFrancesco; Gabrielli, G; Prete, Antonio; Stenström, Per: A Micro-Architectural Power-Saving Technique for D-NUCA Caches. 4th IEEE Workshop on Unique Chips and Systems,

Islam, Mafijul; Själander, Magnus; Stenström, Per: Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors. Microprocessors and Microsystems, Elsevier, 42 (4) pp. 183-196.

Islam, Mafijul; Stenström, Per: Zero Loads: Canceling Load Requests by Tracking Zero Values. IEEE MEDEA,

Jeong, J; Stenström, Per; Dubois, Michel: Simple Penalty-Sensitive Cache Replacement Policies. Journal of Instruction-Level Parallelism,

Stenström, Per: Cache Coherency Protocol Including Generic Transient States.

Proceedings of the 14th IEEE Symp. on High-Performance Computer Architecture. Per Stenström, John Carter, Antonio Gonzalez [editor(s)].

Proceedings of the Third International Conference on High-Performance Embedded Architectures and Compilers. Per Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta [editor(s)].

Stenström, Per: System and Method for Coherence Prediction.

Thuresson, Martin; Själander, Magnus; Stenström, Per: A Flexible Code Compression Scheme using Partitioned Look-Up Tables. Göteborg : Chalmers University of Technology.

Thuresson, Martin; Stenström, Per: Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression. International Conference on Parallel Processing,

Thuresson, Martin; Stenström, Per; Spracklen, Lawrence: Memory Link Compression Schemes: A Value Locality Perspective. IEEE Transactions on Computers,

Waliullah, Mrida Mohammad; Stenström, Per: Efficient Management of Speculative Data in Hardware Transactional Memory Systems. IEEE SAMOS 2008,

Waliullah, Mrida Mohammad; Stenström, Per: Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems. MULTIPROG,

Waliullah, Mrida Mohammad; Stenström, Per: Reducing Roll-back Overhead in Transactional Memory Systems by Checkpointing Conflicting Accesses. 2008 IEEE International Symposium on Parallel and Distributed Processing Systems,

Warg, Fredrik; Stenström, Per: Dual-thread Speculation: A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor.. International Journal of Parallel Programming, 36 (2) pp. 166-183.

Wilhelm, Reinhard; Engblom, Jakob; Ermedahl, Andreas; Holsti, Niklas; Thesing, Stephan; Whalley, David; Bernat, Guillem; Ferdinand, Christian; Heckmann, Reinhold; Mitra, Tulika; Mueller, Frank; Puaut, Isabelle; Puschner, Peter; Stachulat, Jan; Stenström, Per: The worst-case execution-time problem - overview of methods and survey of tools. ACM Trans. Embedded Comput. Syst., 7 (3)

Bardine, Alessandro; Foglia, PieroFrancesco; Gabrielli, G; Stenström, Per; Prete, Antonio: Improving Power Efficiency of D-NUCA Caches. ACM Computer Architecture News,

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Sheeran, Mary; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Stenström, Per: Exposed Datapath for Efficient Computing. 2007 HiPEAC Workshop on Reconfigurable Computing,

Proceedings of the 2007 International Conference on HiPEAC. Koen De Bosschere, David Kaeli, Per Stenström, David Whalley, Theo Ungerer [editor(s)]. Heidelberg : Springer Verlag.

Proceedings of the 2007 ACM International Conference on Computing Frontiers. Michel Dubois, Per Stenström [editor(s)].

Dybdahl, Haakon; Stenström, Per: An Adaptive Shared/Private NUCA Cache Partiotioning Scheme for Chip Multiprocessors. 2007 IEEE International Symp. on High-Performance Computer Architecture,

Hollmann, Jochen; Stenström, Per; Ardö, Anders: Effectiveness of Caching in a Distributed Digital Library.. Journal of Systems Architecture, 53 (7) pp. 403-416.

Islam, Mafijul; Stenström, Per: Energy and Performance Tradeoffs between Instruction Reuse and Trivial Computations for Embedded Applications. IEEE International Symposium on Embedded Computer Systems,

Islam, Mafijul; Busck, Alexander; Engbom, Mikael; Lee, Simji; Dubois, Michel; Stenström, Per: Limits on Thread-Level Speculative Parallelism in Embedded Applications. IEEE INTERACT 2007,

Islam, Mafijul; Busck, Alexander; Engbom, Mikael; Lee, Simji; Dubois, Michel; Stenström, Per: Loop-Level Speculative Parallelism in Embedded Applications. . 2007 International Conference on Parallel Processing,

Llaberia, Jose Maria; Bosque, Ana; Ibanez, Pablo; Stenström, Per; Vinals, Viktor: Characterization of Apache web server with Specweb2005. 2007 IEEE MEDEA,

Stenström, Per; Dubois, Michel; Chen, Jianwei: SimWattch: Integrating complete-system and user-level performance and power simulators . IEEE Micro , 27 (4) pp. 34-48.

Stenström, Per: The Paradigm Shift to Multi-Cores: Opportunities and Challenges. Applied and Computational Mathematics, 6 (2) pp. 253-257.

Transactions on HiPEAC. Per Stenström, Marcelo Cintra, Michael O'Boyle, Francois Bodin, Sally A McKee [editor(s)]. Heidelberg : Springer Verlag.

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. IEEE SAMOS 2007, pp. 18-25.

Vallejo, Enrique; Galluzi, Marco; Cristal, Adrian; Vallejo, F; Beivide, R; Stenström, Per; Smith, Jim; Valero, Mateo: Implicit Transactional Memory in Kilo-Instruction Processors. 12th Asia-Pacific Computer Systems Architecture Conference (ACSAC07),

Waliullah, Mrida Mohammad; Stenström, Per: Efficient Management of Speculative Data in Hardware Transactional Memory Systems. Göteborg : Chalmers University of Technology.

Waliullah, Mrida Mohammad; Stenström, Per: Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems. Göteborg : Chalmers University of Technology.

Waliullah, Mrida Mohammad; Stenström, Per: Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.. ACM Computer Architecture News,

Waliullah, Mrida Mohammad; Stenström, Per: Starvation-Free Transactional Memory System Protocols. . 2007 EUROPAR Conference,

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Sheeran, Mary; Stenström, Per: Exposed Datapath for Efficient Computing. Göteborg : Chalmers University of Technology.

De Bosschere, Koen; Gaydadjiev, Georgi; Martorell, Xavier; Navarro, Nacho; O’Boyle, Mike; Pnevmatikatos, Dionisios; Ramirez, Alex; Sainrat, Pascal; Seznec, Andre; Stenström, Per; Temam, Olivier: High-Performance Embedded Architecture and Compilation Roadmap. Transactions on High-Performance Embedded Architectures and Compilers, 1 (3)

Dybdahl, Haakon; Natvig, Lasse; Stenström, Per: A Cache Replacement Algorithm based on Frequency and Recency for Chip Multiprocessors. . 2006 IEEE MEDEA workshop,

Dybdahl, Haakon; Stenström, Per: A Cache-Partition Aware Replacement Policy for Chip Multiprocessors. . ACM 2006 Conference on High Performance Computing,

Dybdahl, Haakon; Stenström, Per: Enhancing Lower Level Cache Performance by Early Miss Determination and Bypassing. . 11th Asia-Pacific Computer Systems Architecture Conference,

Islam, Mafijul; Stenström, Per: Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations. . 6th IEEE Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation,

Jeong, J; Dubois, Michel; Stenström, Per: Penalty-Sensitive Replacement Policies for Caches.. 2006 ACM Int. Conf. on Computing Frontiers,

Thuresson, Martin; Stenström, Per: Data Link Compression in Multiprocessor Systems. Göteborg : Chalmers University of Technology.

Thuresson, Martin; Spracklen, Lawrence; Stenström, Per: Exploitation of Value Locality for Memory Link Compression. Göteborg : Chalmers University of Technology.

Thuresson, Martin; Stenström, Per: Value-Cache Based Compression Schemes for Multiprocessors. 18th International Conference on Computer Architecture and High Performance Computing,

Waliullah, Mrida Mohammad; Stenström, Per: Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.. 2006 IEEE Workshop on Design, Architecture and Simulation of Chip Multi-Processors ,

Warg, Fredrik; Stenström, Per: Two Threads in the Machine is Better than Eight in the Bush. 18th Symposium on Computer Architecture and High Performance Computing,

Ekman, Magnus; Stenström, Per: A Cost-Effective Memory Organization for Future Servers. IEEE IPDPS,