Bardizbanyan, Alen; Gavin, Peter; Whalley, David; Själander, Magnus; Larsson-Edefors, Per; McKee, Sally A; Stenström, Per: Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB). Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27,

Bardizbanyan, Alen; Själander, Magnus; Whalley, David; Larsson-Edefors, Per: Towards a Performance- and Energy-Efficient Data Filter Cache. Workshop on Optimizations for DSP and Embedded Systems (ODES), Proceedings of International Symposium on Code Generation and Optimization (CGO), Shenzhen, China, Feb. 23-27, ,

Ryman, Erik; Andersson, Stefan; Riesbeck, Johan; Dejanovic, Slavko; Emrich, Anders; Larsson-Edefors, Per: A SiGe 8-Channel Comparator for Application in a Synthetic Aperture Radiometer. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 19-23 2013,

Ryman, Erik; Emrich, Anders; Back Andersson, Stefan; Larsson-Edefors, Per: Development of a Cross-Correlator System for Space-Borne Earth Observation Interferometric Imaging. Proceedings of International Symposium on Space Terahertz Technology, Groningen, The Netherlands, April 8-10 2013,

Subramaniyan, Kasyab P.; Larsson-Edefors, Per: Manufacturable Nanometer Designs using Standard Cells with Regular Layout. Proceedings of International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, March 4-6, 2013,

Azhar, Muhammad Waqar; Själander, Magnus; Hasan, Ali; Vijayashekar, Akshay; Hoang-Thanh, Tung; Ansari, Kashan Khurshid; Larsson-Edefors, Per: Viterbi Accelerator for Embedded Processor Datapaths. 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, 9 - 11 July 2012, pp. 133-140. ISBN/ISSN: 978-076954768-8

Hoang-Thanh, Tung; Larsson-Edefors, Per: Data-Width-Driven Power Gating of Integer Arithmetic Circuits. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, 19-21 August 2012, (Article number 6296479) pp. 237-242. ISBN/ISSN: 978-076954767-1

Larsson-Edefors, Per; Jeppson, Kjell: Training Design Methodology Skills at the Master’s Level. European Workshop on Microelectronics Eduction,

Ryman, Erik; Emrich, Anders; Andersson, Stefan; Riesbeck, Johan; Larsson-Edefors, Per: Application of an Eight-Channel Comparator in a Cross-Correlator for Synthetic Aperture Radiometry. Proceedings of Fourth International Workshop on Analogue and Mixed Signal Integrated Circuits for Space Applications (AMICSA),

Saljooghi, Vahid; Bardizbanyan, Alen; Själander, Magnus; Larsson-Edefors, Per: Configurable RTL Model for Level-1 Caches. Proceedings of NORCHIP, Copenhagen, Denmark, Nov. 11-12, ISBN/ISSN: 978-146732221-8

Subramaniyan, Kasyab P.; Larsson-Edefors, Per: On Regularity and Integrated DFM Metrics. 4th Asia Symposium on Quality Electronic Design (ASQED), Malaysia, July 10-11, 2012 , pp. 211-218. ISBN/ISSN: 978-1-4673-2686-5

Toft, Fredrik; Rousk, Niclas; Mårtensson, Jonas; Forzati, Marco; Olsson, Bengt-Erik; Larsson-Edefors, Per: Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers. IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, 20-23 May 2012, pp. 3234-3237.

Bardizbanyan, Alen; Själander, Magnus; Larsson-Edefors, Per: Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. Proceedings of Reconfigurable Architectures Workshop (RAW), IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp. 322-325 . ISBN/ISSN: 978-076954385-7

Frolov, Nick; Själander, Magnus; Larsson-Edefors, Per; McKee, Sally A: A SAT-Based Compiler for FlexCore. Göteborg : Chalmers University of Technology.

Hidaji, Babak; Alipour, Salar; Subramaniyan, Kasyab P.; Larsson-Edefors, Per: Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 301-306. ISBN/ISSN: 978-076954447-2

Hoang-Thanh, Tung; Saseendran, Vineeth; Siaudinis, Donatas; Larsson-Edefors, Per: Power Gating Multiplier of Embedded Processor Datapath. Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Madonna di Campiglio, Trento; 3 July 2011 through 7 July 2011, pp. 41-44. ISBN/ISSN: 978-1-4244-9136-0

Olsson, Martin; Pihl, Johnny; Andersson, Daniel; Larsson-Edefors, Per: Extracting Vectors from Application Traces for Power Integrity Analysis. Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI). Naples, 8-11 May 2011, pp. 39-42. ISBN/ISSN: 978-145770467-3

Ryman, Erik; Emrich, Anders; Andersson, Stefan; Riesbeck, Johan; Svensson, Lars; Larsson-Edefors, Per: 3.6-GHz 0.2-mW/ch/GHz 65-nm Cross-Correlator for Synthetic Aperture Radiometry. Proceedings of the 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011, San Jose, 19-21 September 2011, ISBN/ISSN: 978-145770222-8

Subramaniyan, Kasyab P.; Ryman, Erik; Själander, Magnus; Hoang-Thanh, Tung; Islam, Mafijul; Larsson-Edefors, Per: FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation. Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), pp. 37-40. ISBN/ISSN: 978-1-4244-9136-0

Azhar, Muhammad Waqar; Hoang-Thanh, Tung; Larsson-Edefors, Per: Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. Proceedings of Euromicro Conference on Digital System Design (DSD), pp. 675-680. ISBN/ISSN: 978-076954171-6

Bardizbanyan, Alen; Subramaniyan, Kasyab P.; Larsson-Edefors, Per: Generation and Exploration of Layouts for Area-Efficient Barrel Shifters. Proceedings of IEEE Computer Society Annual Symp. on VLSI (ISVLSI), pp. 454-455. ISBN/ISSN: 978-076954076-4

Hidaji, Babak; Alipour, Salar; Lidman, Jacob; Subramaniyan, Kasyab P.; Larsson-Edefors, Per: Datapath Interconnect Optimization Engine for Energy-Efficient FlexCore Configurations. Swedish System-on-Chip Conference,

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Transactions on Circuits and Systems I, 57 (12) pp. 3073-3081.

Hoang-Thanh, Tung; Jälmbrant, Ulf; der Hagopian, Erik; Subramaniyan, Kasyab P.; Själander, Magnus; Larsson-Edefors, Per: Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect. Proceedings of IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP),

Jeppson, Kjell; Peterson, Lena; Svensson, Lars; Larsson-Edefors, Per: Implementing Constructive Alignment in a CDIO-oriented Master’s Program in Integrated Electronic System Design. Proceedings of European Workshop on Microelectronics Education, pp. 135-140.

Larsson-Edefors, Per: Teaching Bachelors Electronic Circuits with Electronic Systems Design in Mind. International Journal of Electrical Engineering Education, 47 (3) pp. 263-276.

Qamar, Affaq; Subramaniyan, Kasyab P.; Larsson-Edefors, Per: Impact of Standard Cell Pin Placement on Routing Regularity of HPM Architectures. Swedish System-on-Chip Conference,

Ryman, Erik; Larsson-Edefors, Per; Svensson, Lars; Emrich, Anders; Andersson, Stefan: A Single-Chip 64 Input Low Power High Speed Cross-Correlator for Space Application. European Space Agency Microwave Technology and Techniques Workshop,

Ryman, Erik; Emrich, A.; Embretsen, J.; Riesbeck, J.; Andersson, S.; Larsson-Edefors, Per; Svensson, Lars: Digital Cross-Correlators: Two Approaches. Proceedings of Gigahertz Symposium,

Ryman, Erik; Subramaniyan, Kasyab P.; Hoang-Thanh, Tung; Islam, Mafijul; Själander, Magnus; Larsson-Edefors, Per: FlexTools: Design Space Exploration Tool Chain from C to Physical Implementation. CDNLive! EMEA,

Svensson, Lars; Pihl, Johnny; Andersson, Daniel; Larsson-Edefors, Per: On-chip Power Supply Noise and Its Implications on Timing. Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 389-392. ISBN/ISSN: 978-145030012-4

Waqar, Muhammad; Hoang-Thanh, Tung; Larsson-Edefors, Per: Accelerating Cyclic Redundancy Checking (CRC) Computation in the FlexCore Processor. Swedish System-on-Chip Conference,

Andersson, Daniel; Nilsson, Björn; Pihl, Johnny; Svensson, Lars; Larsson-Edefors, Per: Supply Voltage Drop Study Considering On-Chip Self Inductance of a 32-bit Processor's Power Grid. Proceedings of 13th Workshop on Signal Propagation on Interconnects (SPI),

Axelsson, Emil; Subramaniyan, Kasyab P.; Sheeran, Mary; Larsson-Edefors, Per: Fast Layout Exploration Using the Wired System. Swedish System-on-Chip Conference (SSoCC),

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements. Reconfigurable Architectures Workshop, Proceedings of IEEE International Parallel & Distributed Processing Symposium (IPDPS),

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: High-Speed, Energy-Efficient 2-Cycle Multiply-Accumulate Architecture. Proceedings of IEEE Intl SoC Conference (SoCC), pp. 119-122. ISBN/ISSN: 978-1-4244-5220-0

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: Ultra-Low-Power 2-Cycle Multiply-Accumulate Architecture. Swedish System-on-Chip Conference (SSoCC),

Jeppson, Kjell; Wang, Teng; Liu, Johan; Larsson-Edefors, Per: 3D chip stacking using planarized carbon nanotubes as through-silicon-vias. Swedish System on Chip Conference,

Jälmbrant, Ulf; der Hagopian, Erik; Själander, Magnus; Larsson-Edefors, Per: Design-Time Scheduling for Processor Exploration. Swedish System-on-Chip Conference (SSoCC),

Kimfors, Patrik; Broman, Niklas; Haraldsson, Andreas; Subramaniyan, Kasyab P.; Själander, Magnus; Eriksson, Henrik; Larsson-Edefors, Per: Custom Layout Strategy for Rectangle-Shaped Log-Depth Multiplier Reduction Tree. Proceedings of IEEE International Conference of Electronics, Circuits and Systems,

Ryman, Erik; Larsson-Edefors, Per; Emrich, Anders; Svensson, Lars: High-Performance 64-input Cross-Correlator. Swedish System-on-Chip Conference (SSoCC),

Schilling, Thomas; Själander, Magnus; Larsson-Edefors, Per: Scheduling for an Embedded Architecture with a Flexible Datapath. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 151-156. ISBN/ISSN: 978-1-4244-4408-3

Själander, Magnus; Larsson-Edefors, Per: Multiplication Acceleration through Twin Precision. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17 (9) pp. 1233-1246.

Subramaniyan, Kasyab P.; Axelsson, Emil; Sheeran, Mary; Larsson-Edefors, Per: Layout Exploration of Geometrically Accurate Arithmetic Circuits. Proceedings of IEEE International Conference of Electronics, Circuits and Systems,

Svensson, Lars; Pihl, Johnny; Andersson, Daniel; Nilsson, Björn; Larsson-Edefors, Per: Towards Supply-Grid-Based Derating of Timing Margins. Proceedings of 13th Workshop on Signal Propagation on Interconnects (SPI),

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. Journal of Signal Processing Systems, 57 (1) pp. 5-19.

Andersson, Daniel; Kristiansson, Simon; Svensson, Lars; Larsson-Edefors, Per; Jeppson, Kjell: Noise Interaction Between Power Distribution Grids and Substrate. Proceedings of Intl Symp. on Quality Electronic Design (ISQED), pp. 84-90.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. Proceedings of Intl Symp. on Quality Electronic Design (ISQED), pp. 663-669.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Time-Domain Interconnect Characterisation Flow for Appropriate Model Segmentation. IET Computers & Digital Techniques, 2 (4) pp. 265-274.

Hoang-Thanh, Tung; Själander, Magnus; Larsson-Edefors, Per: Double Throughput MAC for Performance Enhancement of the FlexCore Processor. Swedish System-on-Chip Conference,

Jeppson, Kjell; Peterson, Lena; Svensson, Lars; Bengtsson, Lars; Larsson-Edefors, Per: A New Master's Program in Integrated Electronic System Design. European Workshop on Microelectronics Education, EWME 2008 (Budapest)

Larsson-Edefors, Per: A New Bachelor-Level Electronic Circuits Course at Chalmers University of Technology. Swedish System-on-Chip Conference,

Själander, Magnus; Larsson-Edefors, Per: High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree. Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS),

Själander, Magnus; Larsson-Edefors, Per: The Case for HPM-Based Baugh-Wooley Multipliers. Göteborg : Chalmers University of Technology.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Toward a Systematic Sensitivity Analysis of On-Chip Power Grids Using Factor Analysis. IEEE Workshop on Signal Propagation on Interconnects,

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Sheeran, Mary; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Stenström, Per: Exposed Datapath for Efficient Computing. 2007 HiPEAC Workshop on Reconfigurable Computing,

Do, Minh Quang; Larsson-Edefors, Per; Drazdziulis, Mindaugas: Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays. Göteborg : Chalmers University of Technology.

Do, Minh Quang; Larsson-Edefors, Per; Drazdziulis, Mindaugas: Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits. Göteborg : Chalmers University of Technology. ISBN/ISSN: 2007-07

Do, Minh Quang; Larsson-Edefors, Per; Drazdziulis, Mindaugas: High-Accuracy Architecture-Level Power Estimation for Partitioned Arrays in a 65-nm CMOS BPTM Process. Proceedings of the 10th Euromicro Conference on Digital System Design, Architecture, Methoods and Tools (DSD 2007),

Do, Minh Quang; Drazdziulis, Mindaugas; Larsson-Edefors, Per; Bengtsson, Lars: Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. 8th International Symposium on Quality Electronic Design (ISQED’07), pp. 185 - 191. ISBN/ISSN: 0-7695-2795-7/07

Drazdziulis, Mindaugas; Larsson-Edefors, Per; Svensson, Lars: Overdrive Power-Gating Techniques for Total Power Minimization. IEEE Computer Society Annual Symposium on VLSI,

Själander, Magnus; Larsson-Edefors, Per; Björk, Magnus: A Flexible Datapath Interconnect for Embedded Applications. IEEE Computer Society Annual Symposium on VLSI, pp. 15-20.

Thuresson, Martin; Själander, Magnus; Björk, Magnus; Svensson, Lars; Larsson-Edefors, Per; Stenström, Per: FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. IEEE SAMOS 2007, pp. 18-25.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Interconnect Characterization Flow for Minimal-Segment Model Selection. Norchip Conference,

Björk, Magnus; Själander, Magnus; Svensson, Lars; Thuresson, Martin; Hughes, John; Jeppson, Kjell; Karlsson, Jonas; Larsson-Edefors, Per; Sheeran, Mary; Stenström, Per: Exposed Datapath for Efficient Computing. Göteborg : Chalmers University of Technology.

Brinck, Martin; Eklund, Kristian; Själander, Magnus; Larsson-Edefors, Per: An Efficient FFT Engine Based on Twin-Precision Computation. Swedish System--on-Chip Conference,

Do, Minh Quang; Drazdziulis, Mindaugas; Larsson-Edefors, Per: Architecture-Level Power Estimation and Scaling Trends for SRAM Arrays. Swedish System-on-Chip Conference,

Do, Minh Quang; Drazdziulis, Mindaugas; Larsson-Edefors, Per; Bengtsson, Lars: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. International Symposium on Quality Electronic Design (ISQED),

Eriksson, Henrik; Larsson-Edefors, Per; Sheeran, Mary; Själander, Magnus; Johansson, Daniel; Schölin, Martin: Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity. IEEE Intl Symposium on Circuits and Systems (ISCAS),

Eriksson, Henrik; Larsson-Edefors, Per; Eckerbert, Daniel: Toward Architecture-Based Test-Vector Generation for Timing Verification of Fast Parallel Multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

Alvandpour, A; Larsson-Edefors, Per; Krishnamurthy, R; Soumyanath, K: Fast Dual-Rail Dynamic Logic Style.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Accounting for the Skin Effect during Repeater Insertion. ACM Great Lakes Symposium on VLSI (GLSVLSI),

Själander, Magnus; Drazdziulis, Mindaugas; Larsson-Edefors, Per; Eriksson, Henrik: A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating. IEEE International Symposium on Circuits and Systems, pp. 1654-7.

Själander, Magnus; Larsson-Edefors, Per: A Power-Efficient and Versatile Modified-Booth Multiplier. Swedish System-on-Chip Conference,

Alvandpour, A; Larsson-Edefors, Per; Krishnamurthy, R; Soumyanath, K: Flash [II] - Domino: A Fast Dual-Rail Dynamic Logic Style.

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: Frequency-Dependent Effects in RLC Interconnects. Swedish System-on-Chip Conference,

Andersson, Daniel; Svensson, Lars; Larsson-Edefors, Per: On Skin Effect in On-Chip Interconnects. Intl Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 463-470.

Ciuplys, Dainius; Larsson-Edefors, Per: On Maximum Current Estimation in CMOS Digital Circuits. International Conference on VLSI Design, Mumbai, INDIA. JAN 05-09, 2004 , pp. 658-661.

Do, Minh Quang; Larsson-Edefors, Per; Bengtsson, Lars: Table Based Total Power Consumption Estimation Approach for Architects Do Quang Minh, Per Larsson-Edefors, and Lars Bengtsson, SSoCC’04: Swedish System-on-Chip Conference 2004, April 13-14, Båstad, Sweden, 2004.. SSoCC’04: Swedish System-on-Chip Conference 2004, April 13-14, Båstad, Sweden, 2004.,

Do, Minh Quang; Larsson-Edefors, Per; Bengtsson, Lars: Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. Lecture Notes in Computer Science (LNCS) , Springer Verlag, 3254 (1) pp. 869-878.

Drazdziulis, Mindaugas; Larsson-Edefors, Per: A Comparison of Power Cut-Off Techniques Employed for Ripple Carry Adders in the Presence of Gate Leakage. Swedish System-on-Chip Conference,

Drazdziulis, Mindaugas; Larsson-Edefors, Per; Eckerbert, Daniel; Eriksson, Henrik: A Power Cut-Off Technique for Gate Leakage Suppression. European Solid-State Circuits Conference (ESSCIRC), pp. 171-174.

Drazdziulis, Mindaugas; Larsson-Edefors, Per: Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage. International Symposium on Circuits and Systems (ISCAS), pp. II 745-748.

Eriksson, Henrik; Larsson-Edefors, Per: Dynamic Pass-Transistor Dot Operators for Efficient Parallel-Prefix Adders. International Symposium on Circuits and Systems (ISCAS), pp. II 461-464.

Eriksson, Henrik; Larsson-Edefors, Per: Glitch-Conscious Low-Power Design of Arithmetic Circuits. International Symposium on Circuits and Systems, pp. II 281-284.

Själander, Magnus; Eriksson, Henrik; Larsson-Edefors, Per: An Efficient Twin-Precision Multiplier. International Conference on Computer Design (ICCD), pp. 30-33.

Ciuplys, Dainius; Larsson-Edefors, Per: On Maximum Current Estimation in CMOS Digital Circuits. Proceedings of the Swedish System-on-Chip Conference,

Do, Minh Quang; Bengtsson, Lars; Larsson-Edefors, Per: DSP-PP: A Simulator/Estimator of Power consumption and Performance for Parallel DSP Architectures. Proceedings of the PDCN'03 Symposium (Parallel and Distributed Computing and Networks), Innsbruck, Austria, Feb 10-13, 2002, pp. 767-772, pp. 767-772.

Do, Minh Quang; Bengtsson, Lars; Larsson-Edefors, Per: Models for Power Consumption Estimation in the DSP-PP Simulator. Proceedings of the ISPC'03 International Signal Processing Conference, Dallas, Texas, March 31 - April 3, 2003.,

Drazdziulis, Mindaugas; Larsson-Edefors, Per: A Gate Leakage Reduction Strategy for Future CMOS Circuits. Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003, pp. 317-320. ISBN/ISSN: 0-7803-7995-0

Drazdziulis, Mindaugas; Larsson-Edefors, Per: An Investigation of Gate Leakage for Future CMOS Circuits. Proceedings of the Swedish System-on-Chip Conference,

Eckerbert, Daniel; Larsson-Edefors, Per: A Deep Submicron Power Estimation Methodology Adaptable to Variations Between Power Characterization and Estimation. Proceedings of Asia South-Pacific Design Automation Conference (ASPDAC), Kitakyushu, 21-24 January 2003, pp. 716-719. ISBN/ISSN: 0-7803-7659-5

Eckerbert, Daniel; Svensson, Lars; Larsson-Edefors, Per: A Mixed-Mode Delay-Locked Loop Architecture. Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, 13-15 October 2003, pp. 261-263. ISBN/ISSN: 0-7695-2025-1

Eriksson, Henrik; Larsson-Edefors, Per: Characterizing Ripple-Carry Circuits Using Logical Effort. Proceedings of the Swedish System-on-Chip Conference,

Henriksson, Tomas; Eriksson, Henrik; Larsson-Edefors, Per; Svensson, Christer: Full-Custom vs. Standard-Cell Design Flow - An Adder Case Study. Proceedings of Asia South-Pacific Design Automation Conference (ASPDAC), Kitakyushu, 21-24 January 2003, pp. 507-510. ISBN/ISSN: 0-7803-7659-5

Hughes, John; Jeppson, Kjell; Larsson-Edefors, Per; Sheeran, Mary; Stenström, Per; Svensson, Lars: FlexSoC: Combining Flexibility and Efficiency in SoC Designs. Proceedings of 21st Norchip Conference, Riga, Latvia pp. 52-55.

Larsson-Edefors, Per; Eckerbert, Daniel; Eriksson, Henrik; Svensson, Lars: Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. Proceedings of IEEE Computer Society Annual Symposium on VLSI,

Eriksson, Henrik; Henriksson, Tomas; Larsson-Edefors, Per: Full-Custom vs. Standard-Cell Based Design – An Adder Comparison. Proceedings of the 2002 Swedish System-on-Chip Conference Falkenberg, Sweden, March 18-19, 2002.,